Susan F. Smith

Optimizing package IHS flatness & load for improved thermal/mechanical performance

Physically larger more complex server processors are creating or exacerbating thermal and mechanical challenges in platform design. The larger processors are due, in large part, to the ever increasing core count, increasing integration, and growing I/O performance requirements which pushes pin count demand upwards on the socket thus driving higher processor loading requirements. As a direct result of larger packages and higher loads, the flatness of the package Integrated Heat Spreader (IHS) can be negatively impacted thereby aggravating the current challenges in thermal performance, socket/processor low level contact resistance, and socket solder joint reliability. This paper explores the relationship between processor loading, package IHS flatness, and thermal/mechanical performance at both end of line and end of life. Fundamental learnings were uncovered through investigation of the thermal performance validation of Intels next generation server processors and their corresponding cooling solutions coupled with historical processor thermal/mechanical test data and targeted mechanical sensitivity studies. Thermal degradation focused on IHS flatness quantification, identifying the main drivers triggering degradation post reliability stress, and optimizing key parameters. Utilizing a comprehensive approach encompassing diverse historical thermal data revealed there exists a complex interaction between multiple parameters which can result in a significant impact. It was demonstrated that when parameters were isolated, there was little impact but combining multiple parameters could result in significant thermal degradation. This was a critical and fundamental finding which corroborated that a design must comprehend and test the assembly as a whole to develop retention and cooling solutions that can eliminate or at least minimize both the end of line and end of life thermal resistance.

Challenges and Opportunities in Thermal Management of Multi-Chip Packages

Multi-chip packages (MCPs) based solutions are becoming increasingly adopted as it results in higher signal count, density and enables increasing bandwidth demands and allows for heterogeneous integration [1,2]. However, manufacturing tolerances impose a variability in these stacks which results in new requirements for thermal interface materials. This paper describes the thermal, mechanical, and reliability challenges associated with MCP packages, and highlights need for novel thermal interface materials.Copyright