Susan Felch

Effect of amorphization and carbon co-doping on activation and diffusion of boron in silicon

We investigate the impact of amorphization and C co-implantation on B diffusion and activation properties after conventional spike rapid thermal annealing (RTA). We observe that after complete recrystallization at 600°C the B tail deepens by 5nm (at 5×1018at.∕cm3) due to B diffusion in a-Si. After spike RTA it becomes 12nm deeper with respect to an as-implanted profile, which proves that both diffusion mechanisms in a-Si and c-Si are important. However, the B diffusion in c-Si is sensitive to the fraction of substitutional C incorporated into c-Si. The best junction depth is Xj=16.5nm, with abruptness of 2nm/decade and Rs=583Ω∕◻.

Suppression of phosphorus diffusion by carbon co-implantation

The impact of Si interstitial (Sii) flux suppression on the formation of P junctions by rapid thermal annealing (RTA) is demonstrated. Here we investigate the role of amorphization coupled with C co-implantation on P diffusion and its activation. From experiments on C co-implants in a-Si versus c-Si, we conclude that only a small fraction of C interacts with Si interstitials (Sii). We have demonstrated that optimization of implants followed by spike RTA yields extensions suitable for gate lengths of 30nm, with vertical depth Xj=20nm (taken at 5×1018at.∕cm3), abruptness of 3nm/decade, and Rs=326Ω/◻.

Plasma doping for shallow junctions

In this article we review the characteristics of ultrashallow junctions produced by plasma doping (PLAD). PLAD is one of the alternate doping techniques being developed for sub-0.18 μm devices. Here, we describe results from a wide range of experiments aimed at the production of ultrashallow junctions. For the results shown here, a BF3 plasma was used to provide the dopant ions that were implanted into 150 and 200 mm Si substrates using wafer biases ranging from −0.14 to −5.0 kV. The ultrashallow junctions formed with this technique have been examined with both secondary ion mass spectrometry and electrical profiling techniques. Good sheet resistance uniformity, charging performance, structural quality, and photoresist integrity have been obtained. When PLAD is used in the production of sub-0.2 μm gate length p-metal–oxide–semiconductor field effect transistors, one finds subthreshold swing, off-state leakage, and hot-carrier reliability that are similar to beamline-implanted ones. In addition, higher dri...

Analysis of Dopant Diffusion and Defect Evolution during sub-millisecond Non-melt Laser Annealing based on an Atomistic Kinetic Monte Carlo Approach

n-type dopant diffusion during sub-millisecond (ms) non-melt laser annealing (NLA) is investigated through the experiments and atomistic KMC modeling. Laser-only annealing can improve the n-type dopant activation and achieve shallow junctions. KMC model with vacancy complexes indicates that laser-only annealing for nFET can achieve highly activated junctions and reduce dopant fluctuations in the channel region and that P is an attractive replacement for the As extension with laser-only anneal.Sub-millisecond (ms) non-melt laser annealing (NLA) is investigated through experiments and atomistic KMC modeling. NLA can improve the dopant activation dramatically and achieve shallow junctions. B diffusivity during sub-ms annealing is discussed for the first time. The KMC model with FnVm complexes indicates that the thermal budget of sub-ms annealing is too small for full defect evolution and one possible solution for defect stabilization is F co-implant

Optimization of Sub-Melt Laser Anneal: Performance and Reliability

A thermo-mechanical stress model (TMS) is presented to explain the impact of sub-melt laser anneal (LA) on SiON dielectric and on the overall transistor performance. An Lgmin reduction of 15nm/5nm for nMOS/pMOS over our poly-Si/SiON reference, with 8% capacitance and 10% source and drain resistance (RSD) improvement, is demonstrated. Best device performance and NBTI immunity are reached by lowering the laser power and optimizing the nitrogen and fluorine profile. This minimizes the increase of Si dangling bonds at the SiON/Si interface and the oxide fixed charges, generated by the thermo-mechanical stress (TMS) during the LA fast thermal gradient. The full potential of LA is demonstrated by skipping the RTA. An Lgmin gain of 25nm/20nm is achieved for metal gate nMOS/FUSI gate pMOS devices over the junction RTA reference. Optimal 0.26 fF/mum overlap capacitance values (at Vdd= | 1 | V), 18%/ 23% for nMOS/pMOS lower CV/I product and pMOS improved RSD are demonstrated

Techniques and applications of secondary ion mass spectrometry and spreading resistance profiling to measure ultrashallow junction implants down to 0.5 keV B and BF2

Secondary ion mass spectrometry and spreading resistance profiling techniques have been used to measure dopant profiles and determine electrical activation in ion-implanted samples with effective ion energies as low as 112 eV (i.e., for 0.5 keV BF2). The analytical protocols will be discussed and used to compare the results for samples implanted with ion energies ranging from 0.5 keV (B and BF2) to 8.9 keV (BF2), with and without Ge preamorphization (with and without solid phase epitaxy anneals at 550 °C for 30 min), and finally annealed at 750–1050 °C for 10 s. Limitations of both analytical techniques for ultrashallow junction characterization and areas where improvements are required are discussed.

Reliable and enhanced performances of sub-0.1 /spl mu/m pMOSFETs doped by low biased plasma doping

For the first time, we include low biased plasma doping (LB PLAD) technique for extensions doping within an industrial 0.13 /spl mu/m CMOS process. By comparing to the Ultra-Low Energy Ion Implantation (B/sup +/ and BF/sub 2//sup +/) technique (ULE I/I), plasma doped devices exhibits improved Short Channel Effect (SCE) and subthreshold performances mostly attributed to the good junction characteristics (tradeoff junction depth (X/sub j/)/sheet resistance (R/sub s/)).

Laser-annealed junctions with advanced CMOS gate stacks for 32nm Node: Perspectives on device performance and manufacturability

In this paper, we report on the integration of laser-annealed junctions into a state-of-the-art high-k/metal gate process flow. After implant optimization, we achieve excellent Lg scaling of 15/30 nm over a spike reference, for nMOS and pMOS respectively, without any performance loss. This enables to fabricate transistors with Lgmin meeting the 32 nm node requirement. In addition, we highlight the implication of the metal gate integration flow (ldquogate-firstrdquo vs. ldquogate-lastrdquo) on the junctions design. Also, we demonstrate that a millisecond anneal only (MSA-only) process can fulfill even the stringent junction leakage requirement for low power applications. Finally, based on a combination of physical and electrical characterization, we show for the very first time that micro-uniformities specific to this diffusion-less process have a negligible electrical impact in nominal devices.

Ultrashallow junctions formed by C coimplantation with spike plus submelt laser annealing

A leading candidate for the formation of the ultrashallow junctions needed for Lg⩽45nm devices is the combination of coimplantation of a diffusion-retarding species such as carbon with a high temperature, millisecond annealing process after the conventional spike annealing. C coimplantation with B+ for p-type metal-oxide semiconductor and P+ for n-type metal-oxide semiconductor combined with conventional spike annealing produces reduced junction depths and improved dopant activation and profile abruptness, compared to similar implants without the coimplanted species. Addition of submelt laser annealing may further improve junction activation, but the dominant impact is gate depletion reduction, in that way, delaying the need to introduce metal gates. Devices show that the overlap capacitance is reduced, consistent with the shallower junction depths and reduced lateral diffusion. The improved dopant activation manifests itself in reduced series resistance and improved Ion values. Finally, scanning spreadin...

Co-implantation with conventional spike anneal solutions for 45 nm n-type metal-oxide-semiconductor ultra-shallow junction formation

Co-implantation schemes for sub-65nm n-type extension formation have been explored. These included phosphorous (P) and arsenic (As) implants into crystalline Si as well as combinations using higher energy silicon pre-amorphization implant (PAI) steps together with low energy carbon (C) implantation. Dopant energies were varied between 500eV and 1keV, with C dose of1×1015cm−2 and P and As doses of 7×1014cm−2. The anneal step was a fast ramp-up and ramp-down spike at 1050°C. Comparisons with dopant-only implants or with PAI and dopant only showed these two schemes to give deeper, more gradual and less well activated junctions than when combined with C. The best result was obtained using a 25keV Si PAI, 6keV C and 1keV P, resulting in a junction depth of 20.5nm at 1×1019cm−3, and Rs=318Ω∕◻ and a 3nm∕dec trailing slope.