Susan Marya Schober

A charge transfer-based high performance, ultra-low power PLL charge pump

This paper presents a high performance, ultra-low power scalable charge pump (CP) design for analog phase locked loops (PLLs). The compact CP circuit uses 4 minimum-sized transistor switches and a relatively small capacitor for transferring charge within the PLL to adjust the voltage controlled oscillator (VCO) frequency. Unlike the state of the art, the proposed CP design does not use current mirrors, has the ability to operate at very low voltages, and does not suffer from traditional mismatch errors due to its unique design. The fast switching action of the proposed CP allows for the use of a no-added delay D-flip flop (DFF) based phase-frequency detector (PFD) resulting in reduced PLL control loop delay and very low reference spurs in a PLL design. The proposed CP has been fabricated with a 1-10GHz PLL in TSMC all-digital 40nm CMOS process and physically tested with a variable 0.5-1.2V supply and a 50MHz-1GHz reference frequency. The charge pump has an active area of 0.0004mm2, consumes on average 250pW power, and has a 0.1-0.3° phase error, depending on the PLL frequency of operation.

A 1.25mW 0.8–28.2GHz charge pump PLL with 0.82ps RMS jitter in all-digital 40nm CMOS

This paper presents a wide-operating range analog phase locked loop (PLL) constructed from all-digital integrated circuit (IC) process components. Specifically, this work introduces 2 cutting-edge, scalable analog circuit designs for a charge pump (CP) and a voltage controlled oscillator (VCO). The ultra-low power and highly accurate CP circuit uses 6 minimum-sized transistors, a small metal interconnect capacitor, and, unlike the state-of-the-art, no current mirrors. The ring VCO has a reconfigurable, expandable structure and is capacitively tunable allowing for an exceptionally large frequency operating range of 0.8 to 28.2GHz making it suitable for variety of wireless and wireline applications. The PLL has been fabricated in a TSMC 40nm all-digital CMOS process and physically tested with a 0.5-1.2V supply. The fabricated PLL has an area of 0.0048mm2, consumes a maximum of 1.25mW, and has a 0.82 ±0.0275ps RMS jitter over the entire operating range.

A capacitively phase-coupled low noise, low power 0.8-to-28.2GHz quadrature ring VCO in 40nm CMOS

This paper presents a novel tunable wide-operating range capacitively phase-coupled low noise, low power ring-based voltage controlled oscillator (VCO) for use in multi-GHz phase-locked loops (PLLs). The basic building blocks of the ring oscillator (RO) design are discussed along with a technique to expand the VCO to a variety of phases and frequencies without the use of physical inductors. Improved performance with minimal phase noise are achieved in this ring VCO design through distributed passive-element injection locking (IL) of the staged phases via a network of symmetrically placed metal interconnect capacitors. Using this method, a 0.8-to-28.2 GHz quadrature ring VCO was designed, fabricated, and physically tested with a PLL in an all-digital 40nm TSMC CMOS process. Most notably the proposed quadrature VCO occupies an area of 0.0024mm2, consumes a power of 0.88mW at a 1.0V supply voltage, and possesses a phase noise of -124.5dBc/Hz at the 10MHz offset for a carrier frequency of 28.0GHz.