John Choma

A supply-noise-insensitive CMOS PLL with a voltage regulator using DC-DC capacitive converter

A 500-MHz supply-noise-insensitive CMOS phase-locked loop (PLL) with a voltage regulator using a capacitive dc-dc converter (VRCC) achieves a jitter level of 30-ps RMS for quiet supply, and 42-ps RMS for 600-mV supply noise, with a locking range of 110 to 850 MHz. The worst-case power supply noise rejection (PSNR) using the VRCC shows -45 dB in the mid-frequency band. The circuit is fabricated in a 0.35-/spl mu/m 3.3-V standard digital CMOS process and occupies 2.3 mm/sup 2/. The power consumption at 3.3 V including buffer is 42 mW at 500 MHz.

A continuous-time common-mode feedback circuit (CMFB) for high-impedance current-mode applications

A continuous-time common-mode feedback circuit (CMFB) is presented. A two-stage high-gain architecture is used to stabilize and minimize the offset of the common-mode voltage. A long-channel differential-difference amplifier (DDA) input stage enables this CMFB circuit to have a wide input voltage range without a serious linearity problem. A special compensation scheme enables this circuit to be used in high-impedance current-mode systems without a stability problem. This circuit has been implemented within a continuous-time switched-current /spl Sigma//spl Delta/ modulator in a 2 /spl mu/m CMOS process. It achieves a /spl plusmn/1 V input voltage range with an active area of 100 /spl mu/m/spl times/60 /spl mu/m and a power dissipation of 270 /spl mu/W from a single 5 V power supply.

Gyrator-Based Synthesis of Active On-Chip Inductances

A detailed analysis of a gyrator-based inductance using operational transconductance amplifiers is presented. The advantages of such integrated inductances over passive spirals include higher quality factors and the ability to tune inductance values. Design equations are derived using a practical high-frequency model of each transconductor, and operating constraints are provided to mitigate the effects of parasitics and to ensure optimal performance and stability.

A high-speed fully differential current switch

A high-speed differential-mode current switch is presented. The clock-feedthrough effect is reduced by swing-reduced drivers (SRDs) and neutralized by dummy transistors. With the use of SRDs, the switching transistors never operate in the triode region, which provides good matching of capacitance between the switching transistors and dummy transistors. The SRDs also reduce the possible large current spikes on the outputs of the current switch. Analysis shows this current switch is ideal for high-speed current-mode signal processing. A continuous-time switched-current /spl Sigma//spl Delta/ modulator using these current switches has been implemented in a 2 /spl mu/m CMOS process and achieved a 59 dB dynamic range with a 50 MHz clock.

A continuous-time common-mode feedback circuit (CMFB) for high-impedance current mode application

A continuous-time common-mode feedback circuit (CMFB) is presented. A two-stage high-gain architecture is used to minimize the offset of the common-mode voltage. A special compensation scheme enables this circuit to be used in high-impedance current-mode systems without a stability problem. Simulation and testing results show the superior performance of this circuit. It is proven to be an ideal common-mode feedback circuit for systems which require an accurate and stable common-mode voltage. This circuit has been implemented in a continuous-time switched-current /spl Sigma//spl Delta/ modulator with a 2 /spl mu/m CMOS process. With a 50 MHz clock, the modulator has achieved a 60 dB dynamic range in a 1 MHz bandwidth.

A Dynamic Thermal Management Circuit for System-On-Chip Designs

A novel fully integrated dynamic thermal management circuit for system-on-chip design is proposed. Instead of worst-case thermal management used in conventional systems, this design yields continual monitoring of thermal activity and reacts to specified conditions. With the above system, we are able to incorporate on-chip power/speed modulation and integrated multi-stage fan controllers, which allows us to achieve nominal power dissipation and ensure operation within specification. Both architecture and circuitry are optimized for modern system-on-chip designs. This design yields intricate control and optimal mangement with little system overhead and minimum hardware requirements, as well as provides the flexibility to support different thermal mangement algorithms.

The design and analysis of a RF CMOS bandpass filter

A high-Q filter capable of operating in the GHz range is proposed. This filter, which is suitable for RF applications, utilizes two effective Q-enhancement techniques to circumvent the low-Q characteristics inherent in the circuit. Simulation results employing standard 0.5 /spl mu/m CMOS technology have successfully verified that the center frequency tuning and hybrid Q-tuning techniques operate between 625 MHz and 1.68 GHz center frequencies with Q ranging from 12 to over 300. Two tunable bandpass filters with center frequencies at 876 MHz and 1.68 GHz have been designed to have 37 dB and 31.4 dB voltage gain, -30 dBm and -31 dBm IIP3, and 4.8 dB and 5.5 dB NF, respectively. Both filters have quality factors equal to 33 and power dissipation is equal to 24.3 mW.

Design of low jitter PLL for clock generator with supply noise insensitive VCO

Supply and substrate noise tend to cause the output clock of PLLs to jitter from their ideal timing. The design of a low jitter PLL has become challenging because of the many design trade-offs between noise and bandwidth. In order to achieve a low jitter PLL design, fully differential signal and control paths of the VCO are maintained. Also, a proposed bandgap regulator helps to achieve high common mode rejection of supply and substrate noise. This proposed bandgap reference serves to reduce oscillator supply and temperature sensitivities and to suppress low/high frequency noise by isolation from supply noise. The simulated oscillator supply noise sensitivity is less than 1 percent/V. Oscillator temperature sensitivity is 500 ppm//spl deg/C in the range of 0 to 100/spl deg/C. Oscillator frequency range is 25 MHz to 400 MHz using a MOSIS 0.8 /spl mu/m CMOS process. The clock skew is less than 60 ps with a peak-to-peak jitter of less than 100 ps for a 200 MHz PLL clock frequency.

Current-mode approach for wide-gain bandwidth product architecture

This paper describes the architectures of a fully differential input/single-ended output wide-band high-gain current-mode comparator and amplifier. Both architectures employ a current conveyor as the primary means of current-mode operation. The proposed comparator circuit delivers extremely high gain and wide bandwidth by employing cascode complementary gain stages and feedforward compensation techniques, respectively. The closed-loop voltage amplifier, using the proposed current-mode techniques, can improve upon the gain-bandwidth product when compared to conventional voltage-mode techniques. Computer simulation results show 135 dB of gain and 100 MHz bandwidth for such an amplifier.

CMOS 12 bits 50kS/s micropower SAR and dual-slope hybrid ADC

In this paper a 12 bits 50kS/s micropower hybrid ADC is proposed for biomimetic microelectronic systems using 0.18um CMOS process. The hybrid ADC combines SAR and dual-slope architectures to achieve 12 bits, power consumption 60uW, and small silicon die size. This hybrid ADC shows very good figure-of-merits (FOM) on both power consumption and silicon die size compared with conventional low power SAR ADC. A fully differential GmC integrator is proposed for the dual-slope operation with low voltage discrete-time CMFB.