Suying Yao

A 128-Stage Analog Accumulator for CMOS TDI Image Sensor

The impacts of parasitic phenomenon on the performance of the analog accumulator in CMOS TDI image sensor are analyzed in this paper, and a modified accumulator with decoupling capacitor Cd to combat the parasitic phenomenon is also proposed. A 128-stage modified accumulator is designed and simulated. A prototype 1024 × 128 CMOS TDI image sensor with the 128-stage modified accumulator is fabricated in 0.18- μm one-poly four-metal 1.8 V/3.3 V CMOS technology. With a line rate of 3875 lines/s, at 128 stages the measured sensitivity and SNR improvement of the fabricated sensor are 617.1 V/lux·s and 16.6 dB respectively. The simulation and experiment results have proved the effectiveness of the decoupling capacitor Cd when combating the parasitic phenomenon in the analog accumulator. The proposed modified accumulator is suitable for application in CMOS TDI image sensor with high stages.

Thirty Two-Stage CMOS TDI Image Sensor With On-Chip Analog Accumulator

This brief presents a 32-stage CMOS time delay integration image sensor with on-chip column parallel analog accumulator. Temporal oversampling technique is applied in the sensor to realize synchronous signal capturing. A column parallel analog accumulator with layout size of 0.09 mm2 is integrated at both sides of pixel array. Through adopting input-offset storing technique, a column fixed pattern noise because of the amplifiers offset variations is reduced by the accumulator. The accumulator also acts as a pixel noise canceller. The fabricated chip in 0.18- μm one-poly four-metal 1.8/3.3-V CMOS technology achieves the maximum line rate of 3875 lines/s. The measured signal-to-noise ratio of the fabricated sensor is improved on average by 11.9 dB at 16 stages and 14.2 dB at 32 stages. The presented sensor is suitable for application in low illumination, high scanning speed, and remote sensing systems.

Copyright protection for digital image in wireless sensor network

In wireless sensor network (WSN), digital image data are transported in uncontrolled and possibly hostile environment. Thus, copyright protection has drawn much attention in behalf of the originators of the sensing data in wireless transmission. Traditional security schemes are computationally expensive, because they introduce overhead which shortens the life of the image sensors. In comparison with traditional security techniques, watermark schemes are usually light weight and do not require extensive computing and power resources. Thus they can be attractive options for wireless sensor applications. According to the feature of DCT coefficients, this paper proposes a real-time robust watermark algorithm whose coefficients are obtained through experiments. To make the watermark more robust, we embed the watermark into the low-frequency coefficients of DCT. Experimental results show that this algorithm is real-time, imperceptible and robust, thereby it can satisfy with the wireless network transmission requirements.

A 12-bit high-speed column-parallel two-step single-slope analog-to-digital converter (ADC) for CMOS image sensors.

A 12-bit high-speed column-parallel two-step single-slope (SS) analog-to-digital converter (ADC) for CMOS image sensors is proposed. The proposed ADC employs a single ramp voltage and multiple reference voltages, and the conversion is divided into coarse phase and fine phase to improve the conversion rate. An error calibration scheme is proposed to correct errors caused by offsets among the reference voltages. The digital-to-analog converter (DAC) used for the ramp generator is based on the split-capacitor array with an attenuation capacitor. Analysis of the DACs linearity performance versus capacitor mismatch and parasitic capacitance is presented. A prototype 1024 × 32 Time Delay Integration (TDI) CMOS image sensor with the proposed ADC architecture has been fabricated in a standard 0.18 μm CMOS process. The proposed ADC has average power consumption of 128 μW and a conventional rate 6 times higher than the conventional SS ADC. A high-quality image, captured at the line rate of 15.5 k lines/s, shows that the proposed ADC is suitable for high-speed CMOS image sensors.

Leakage current study and relevant defect localization in integrated circuit failure analysis

Abstract The purpose of integrated circuit (IC) failure analysis (FA) is to find and to explain failure root cause and mechanism, which helps IC designer and manufacturer to improve design and process. Leakage current presence within circuit is the main failure root cause among the FA cases, although the leakage currents within different circuits can stimulate a variety of IC failure modes. It is significant to study the leakage currents within ICs and to localize relevant defects quickly and accurately by the combination of some complementary FA techniques. However, it is difficult to identify the original leakage current from the consequential leakage currents and to locate the relevant defect. In this paper, we explain the shape and location of a photon emission spot induced by an original leakage current is different from the one induced by a consequential leakage current. In a general case, and not only in this photon emission spot case, a method is elaborated to identify the original leakage current from the consequential leakage currents and to exactly locate the relevant defect by the combination of some complementary FA techniques. Some other functional failure cases will be studied to demonstrate adaptation and interest of this general method.

Analysis of noise of current accumulator in Time-Delay-Integration CMOS image sensor

The noise of the current accumulator is analyzed. And a model of Time-Delay-Integration (TDI) CMOS image sensor is presented, which is used to analyze the noise performance. In this model, input signals are accumulated 4 times by the type of current and then converted to digital signals to accomplish the other accumulation by 32 times, i.e., 4×32 accumulation mode. The noise, which includes switch charge injection, sample noise and KT/C noise, is considered in this model. The major source of the noise and the relationship between noise and sample capacitance are evaluated through the model simulation. The results indicate that the total noise can be restrained by increasing sample capacitance. When the input signal is arranging from 0µA to 100µA, the accuracy of the current accumulator can be 11bits by using 1pF sample capacitor. And the SNR of the output signal can be increased by 20.38dB which is close to the ideal result.

Preparation of micro fluidic chip based on SU-8 mold

As the silicon mold has rough edges, microchip is not conducive to fluid movement. In this paper, mold was produced by SU-8, and a set of production process was given. Then this paper made anti-stick layer on the mold, in order to improve mold re-use rate. Author discussed the impact of curing temperature and the ratio of PDMS and curing agent on the device, and does modification on casting PDMS, then seal to complete the microarray.

An efficient architecture for 2-D lifting-based discrete wavelet transform

This paper proposes an efficient VLSI architecture for implementation of 2-D lifting-based discrete wavelet transform (DWT). The whole architecture was optimized in efficient pipeline and parallel design way to speed up and achieve higher hardware utilization. Adopted time division multiplex (TDM) design to realize the prediction step and update step using the same architecture, which reduced the size of the circuit. Exploited embedded mirror symmetric boundary extension technique to optimize the architecture for 1-D DWT. The architecture was coded in Verilog HDL, implemented in a FPGA, and verified by a real-time platform which comprises a CMOS image sensor, a FPGA and a PC.

A Two-Step Analog Accumulator for CMOS TDI Image Sensor With Temporal Undersampling Exposure Method

A two-step analog accumulator structure, fit for CMOS time-delay integration image sensor, is proposed to combat the impacts of parasitic phenomenon of the traditional one-step analog accumulator. To implement the two-step accumulation, the exposure signals are divided into groups. The synchronous signals in each group are integrated in step1 integrators, which are designed based on the switched-capacitor amplifier. Then, the integral signals from step1 are integrated in step2 integrators. The temporal undersampling exposure method is adopted in the sensor to reduce the number of integrators. Two versions of a prototype 64-stage two-step accumulator, with and without the decoupling capacitance Cd, are designed and fabricated in 0.18-μm one-poly four-metal 1.8 V/3.3 V CMOS technology. With an 8×8 stepping pattern, the signal-to-noise ratio improvements of the two versions are 17.278 and 17.192 dB at 64 stages, respectively, while the ideal value is 18.062 dB. The experimental results have proved the effectiveness of the two-step structure in combating the parasitic phenomenon and made the analog accumulator with higher stage realizable.

An Event-Based Neurobiological Recognition System with Orientation Detector for Objects in Multiple Orientations

A new multiple orientation event-based neurobiological recognition system is proposed by integrating recognition and tracking function in this paper, which is used for asynchronous address-event representation (AER) image sensors. The characteristic of this system has been enriched to recognize the objects in multiple orientations with only training samples moving in a single orientation. The system extracts multi-scale and multi-orientation line features inspired by models of the primate visual cortex. An orientation detector based on modified Gaussian blob tracking algorithm is introduced for object tracking and orientation detection. The orientation detector and feature extraction block work in simultaneous mode, without any increase in categorization time. An addresses lookup table (addresses LUT) is also presented to adjust the feature maps by addresses mapping and reordering, and they are categorized in the trained spiking neural network. This recognition system is evaluated with the MNIST dataset which have played important roles in the development of computer vision, and the accuracy is increased owing to the use of both ON and OFF events. AER data acquired by a dynamic vision senses (DVS) are also tested on the system, such as moving digits, pokers, and vehicles. The experimental results show that the proposed system can realize event-based multi-orientation recognition. The work presented in this paper makes a number of contributions to the event-based vision processing system for multi-orientation object recognition. It develops a new tracking-recognition architecture to feedforward categorization system and an address reorder approach to classify multi-orientation objects using event-based data. It provides a new way to recognize multiple orientation objects with only samples in single orientation.