Kaiming Nie

A 128-Stage Analog Accumulator for CMOS TDI Image Sensor

The impacts of parasitic phenomenon on the performance of the analog accumulator in CMOS TDI image sensor are analyzed in this paper, and a modified accumulator with decoupling capacitor Cd to combat the parasitic phenomenon is also proposed. A 128-stage modified accumulator is designed and simulated. A prototype 1024 × 128 CMOS TDI image sensor with the 128-stage modified accumulator is fabricated in 0.18- μm one-poly four-metal 1.8 V/3.3 V CMOS technology. With a line rate of 3875 lines/s, at 128 stages the measured sensitivity and SNR improvement of the fabricated sensor are 617.1 V/lux·s and 16.6 dB respectively. The simulation and experiment results have proved the effectiveness of the decoupling capacitor Cd when combating the parasitic phenomenon in the analog accumulator. The proposed modified accumulator is suitable for application in CMOS TDI image sensor with high stages.

Thirty Two-Stage CMOS TDI Image Sensor With On-Chip Analog Accumulator

This brief presents a 32-stage CMOS time delay integration image sensor with on-chip column parallel analog accumulator. Temporal oversampling technique is applied in the sensor to realize synchronous signal capturing. A column parallel analog accumulator with layout size of 0.09 mm2 is integrated at both sides of pixel array. Through adopting input-offset storing technique, a column fixed pattern noise because of the amplifiers offset variations is reduced by the accumulator. The accumulator also acts as a pixel noise canceller. The fabricated chip in 0.18- μm one-poly four-metal 1.8/3.3-V CMOS technology achieves the maximum line rate of 3875 lines/s. The measured signal-to-noise ratio of the fabricated sensor is improved on average by 11.9 dB at 16 stages and 14.2 dB at 32 stages. The presented sensor is suitable for application in low illumination, high scanning speed, and remote sensing systems.

A 12-bit high-speed column-parallel two-step single-slope analog-to-digital converter (ADC) for CMOS image sensors.

A 12-bit high-speed column-parallel two-step single-slope (SS) analog-to-digital converter (ADC) for CMOS image sensors is proposed. The proposed ADC employs a single ramp voltage and multiple reference voltages, and the conversion is divided into coarse phase and fine phase to improve the conversion rate. An error calibration scheme is proposed to correct errors caused by offsets among the reference voltages. The digital-to-analog converter (DAC) used for the ramp generator is based on the split-capacitor array with an attenuation capacitor. Analysis of the DACs linearity performance versus capacitor mismatch and parasitic capacitance is presented. A prototype 1024 × 32 Time Delay Integration (TDI) CMOS image sensor with the proposed ADC architecture has been fabricated in a standard 0.18 μm CMOS process. The proposed ADC has average power consumption of 128 μW and a conventional rate 6 times higher than the conventional SS ADC. A high-quality image, captured at the line rate of 15.5 k lines/s, shows that the proposed ADC is suitable for high-speed CMOS image sensors.

A Fixed-Pattern Noise Correction Method Based on Gray Value Compensation for TDI CMOS Image Sensor

In order to eliminate the fixed-pattern noise (FPN) in the output image of time-delay-integration CMOS image sensor (TDI-CIS), a FPN correction method based on gray value compensation is proposed. One hundred images are first captured under uniform illumination. Then, row FPN (RFPN) and column FPN (CFPN) are estimated based on the row-mean vector and column-mean vector of all collected images, respectively. Finally, RFPN are corrected by adding the estimated RFPN gray value to the original gray values of pixels in the corresponding row, and CFPN are corrected by subtracting the estimated CFPN gray value from the original gray values of pixels in the corresponding column. Experimental results based on a 128-stage TDI-CIS show that, after correcting the FPN in the image captured under uniform illumination with the proposed method, the standard-deviation of row-mean vector decreases from 5.6798 to 0.4214 LSB, and the standard-deviation of column-mean vector decreases from 15.2080 to 13.4623 LSB. Both kinds of FPN in the real images captured by TDI-CIS are eliminated effectively with the proposed method.

Analysis of noise of current accumulator in Time-Delay-Integration CMOS image sensor

The noise of the current accumulator is analyzed. And a model of Time-Delay-Integration (TDI) CMOS image sensor is presented, which is used to analyze the noise performance. In this model, input signals are accumulated 4 times by the type of current and then converted to digital signals to accomplish the other accumulation by 32 times, i.e., 4×32 accumulation mode. The noise, which includes switch charge injection, sample noise and KT/C noise, is considered in this model. The major source of the noise and the relationship between noise and sample capacitance are evaluated through the model simulation. The results indicate that the total noise can be restrained by increasing sample capacitance. When the input signal is arranging from 0µA to 100µA, the accuracy of the current accumulator can be 11bits by using 1pF sample capacitor. And the SNR of the output signal can be increased by 20.38dB which is close to the ideal result.

A Low Power Digital Accumulation Technique for Digital-Domain CMOS TDI Image Sensor

In this paper, an accumulation technique suitable for digital domain CMOS time delay integration (TDI) image sensors is proposed to reduce power consumption without degrading the rate of imaging. In terms of the slight variations of quantization codes among different pixel exposures towards the same object, the pixel array is divided into two groups: one is for coarse quantization of high bits only, and the other one is for fine quantization of low bits. Then, the complete quantization codes are composed of both results from the coarse-and-fine quantization. The equivalent operation comparably reduces the total required bit numbers of the quantization. In the 0.18 µm CMOS process, two versions of 16-stage digital domain CMOS TDI image sensor chains based on a 10-bit successive approximate register (SAR) analog-to-digital converter (ADC), with and without the proposed technique, are designed. The simulation results show that the average power consumption of slices of the two versions are 6.47×10-8 J/line and 7.4×10-8 J/line, respectively. Meanwhile, the linearity of the two versions are 99.74% and 99.99%, respectively.

A real-time digital calibration scheme for the cyclic ADC

A digital calibration scheme to correct the nonlinearity caused by finite amplifier gain and capacitor mismatch for the cyclic analog-to-digital converter (ADC) is presented. The calibration block of correcting the weight of the jumping points is implemented in which adders and registers are utilized without multipliers to reduce the silicon area cost. Each calibration block is shared by five ADCs. Ten switches are added into the 1.5-bit multiplying digital-to-analog converter to choose the test input signal and set the value of the most significant bit for measuring the heights of the jumping points. The capacitor mismatch and gain errors are measured as one error, and then the weight of the jumping points is compensated in the digital domain to improve the linearity of the ADC. Designed in a 0.18µm CMOS technology, the silicon area cost of each ADC is 0.03×1.7mm2 and the power consumption is 0.56mW at a supply voltage of 1.8V. The simulation results show that the calibration improves SNDR to 83.73dB from 55.13dB with 1% capacitance mismatch, and the calibration needs three conversion cycles which makes it real-time to obtain the changing error parameters during normal operation.

A Two-Step Analog Accumulator for CMOS TDI Image Sensor With Temporal Undersampling Exposure Method

A two-step analog accumulator structure, fit for CMOS time-delay integration image sensor, is proposed to combat the impacts of parasitic phenomenon of the traditional one-step analog accumulator. To implement the two-step accumulation, the exposure signals are divided into groups. The synchronous signals in each group are integrated in step1 integrators, which are designed based on the switched-capacitor amplifier. Then, the integral signals from step1 are integrated in step2 integrators. The temporal undersampling exposure method is adopted in the sensor to reduce the number of integrators. Two versions of a prototype 64-stage two-step accumulator, with and without the decoupling capacitance Cd, are designed and fabricated in 0.18-μm one-poly four-metal 1.8 V/3.3 V CMOS technology. With an 8×8 stepping pattern, the signal-to-noise ratio improvements of the two versions are 17.278 and 17.192 dB at 64 stages, respectively, while the ideal value is 18.062 dB. The experimental results have proved the effectiveness of the two-step structure in combating the parasitic phenomenon and made the analog accumulator with higher stage realizable.

Modeling and simulation of TDI CMOS image sensors

In this paper, a mathematical model of TDI CMOS image sensors was established in behavioral level through MATLAB based on the principle of a TDI CMOS image sensor using temporal oversampling rolling shutter in the along-track direction. The geometric perspective and light energy transmission relationships between the scene and the image on the sensor are included in the proposed model. A graphical user interface (GUI) of the model was also established. A high resolution satellitic picture was used to model the virtual scene being photographed. The effectiveness of the proposed model was verified by computer simulations based on the satellitic picture. In order to guide the design of TDI CMOS image sensors, the impacts of some parameters of TDI CMOS image sensors including pixel pitch, pixel photosensitive size, and integration time on the performance of the sensors were researched through the proposed model. The impacts of the above parameters on the sensors were quantified by sensor’s modulation transfer function (MTF) of the along-track direction, which was calculated by slanted-edge method. The simulation results indicated that the TDI CMOS image sensor can get a better performance with smaller pixel photosensitive size and shorter integration time. The proposed model is useful in the process of researching and developing a TDI CMOS image sensor.

A fast correlated multiple sampling technique based on 12-bit SAR ADC with digital calibration for low-noise CMOS image sensor

A fast multiple correlated sampling technique based on successive approximation register analog-to-digital converter (SAR ADC) for low-noise CMOS image sensors is proposed in this paper. During the whole operation of the fast multiple correlated sampling, m-times samplings and conversions are achieved. The SAR ADC completes a full conversion in the first conversion and only converts lower M bits in the following conversions to decrease the total conversion time. The influences of three factors, the number of samplings, the number of bits converted in the repeated conversions and the resolution of ADC, on the fast multiple correlated sampling are analyzed in detail. A 12-bit SAR ADC with digital calibration based one bit redundancy to relieve the requirement of the capacitor mismatch is designed in the fast correlated multiple sampling technique. The proposed correlated multiple sampling technique is implemented and simulated through standard 180nm CMOS process. The SAR ADC achieves 72.55dB signal-to-noise-and-distortion ratio after digital calibration. The simulation results match the analysis well. Readout noise in CMOS image sensors can be reduced by the factor of m effectively with appropriate M based on the fast correlated multiple sampling technique. The total conversion time is decreased effectively, and it is only 10.9s for 16 times fast correlated multiple sampling. The fast multiple correlated sampling technique based on SAR ADC is suitable for low-noise and high-speed CMOS image sensor.