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Dive into the research topics where Suyog Gupta is active.

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Featured researches published by Suyog Gupta.


Journal of Applied Physics | 2013

Achieving direct band gap in germanium through integration of Sn alloying and external strain

Suyog Gupta; Blanka Magyari-Köpe; Yoshio Nishi; Krishna C. Saraswat

GeSn is predicted to exhibit an indirect to direct band gap transition at alloy Sn composition of 6.5% and biaxial strain effects are investigated in order to further optimize GeSn band structure for optoelectronics and high speed electronic devices. A theoretical model has been developed based on the nonlocal empirical pseudopotential method to determine the electronic band structure of germanium tin (GeSn) alloys. Modifications to the virtual crystal potential accounting for disorder induced potential fluctuations are incorporated to reproduce the large direct band gap bowing observed in GeSn alloys.


international electron devices meeting | 2011

GeSn technology: Extending the Ge electronics roadmap

Suyog Gupta; Robert Chen; Blanka Magyari-Köpe; Hai Lin; Bin Yang; Aneesh Nainani; Yoshio Nishi; James S. Harris; Krishna C. Saraswat

First principles study showed indicated band gap of Ge can be tuned by alloying with Sn and metastable GeSn alloys can be synthesized at or above room temperature. Subsequently, high quality GeSn layers were grown using low temperature MBE. PL indicated good crystal quality of GeSn material with a reduced direct bandgap. Challenges involved in CMOS processing on GeSn were addressed through effective surface cleaning and a low thermal budget process flow. To the best of our knowledge this work is the first demonstration of a high-κ pMOSFET using 3% GeSn as channel material showing 20% improvement in hole mobility compared to Ge. Alloying Ge with Sn has thus been shown as a performance booster for Ge based devices. Further improvements in material quality and incorporation of higher substitutional Sn, coupled with strain and bandgap engineering, significant performance gains can be achieved from this alloy system.


Nano Letters | 2014

Demonstration of a Ge/GeSn/Ge Quantum-Well Microdisk Resonator on Silicon: Enabling High-Quality Ge(Sn) Materials for Micro- and Nanophotonics

Robert Chen; Suyog Gupta; Yi-Chiau Huang; Yijie Huo; Charles W. Rudy; Errol Antonio C. Sanchez; Yihwan Kim; Theodore I. Kamins; Krishna C. Saraswat; James S. Harris

We theoretically study and experimentally demonstrate a pseudomorphic Ge/Ge0.92Sn0.08/Ge quantum-well microdisk resonator on Ge/Si (001) as a route toward a compact GeSn-based laser on silicon. The structure theoretically exhibits many electronic and optical advantages in laser design, and microdisk resonators using these structures can be precisely fabricated away from highly defective regions in the Ge buffer using a novel etch-stop process. Photoluminescence measurements on 2.7 μm diameter microdisks reveal sharp whispering-gallery-mode resonances (Q > 340) with strong luminescence.


IEEE Transactions on Electron Devices | 2014

7-nm FinFET CMOS Design Enabled by Stress Engineering Using Si, Ge, and Sn

Suyog Gupta; Victor Moroz; Lee Smith; Qiang Lu; Krishna C. Saraswat

Bandgap and stress engineering using group IV materials-Si, Ge, and Sn, and their alloys are employed to design a FinFET-based CMOS solution for the 7-nm technology node and beyond. A detailed simulation study evaluating the performance of the proposed design is presented. Through the use of a common strain-relaxed buffer layer for p- and n-channel MOSFETs and a careful selection of source/drain stressor materials, the CMOS design is shown to achieve performance benefits over strained Si, meet the IOFF requirements, and provide a path for continued technology scaling.


IEEE Electron Device Letters | 2013

Hole Mobility Enhancement in Compressively Strained

Suyog Gupta; Yi-Chiau Huang; Yihwan Kim; Errol Antonio C. Sanchez; Krishna C. Saraswat

Germanium tin (GeSn) pMOSFETs with channel Sn composition of 7% are fabricated using a low thermal budget process. GeSn pMOSFETs show enhancement in hole mobility over control Ge devices by 85% in high inversion charge density regime. Hole mobility improvement observed in GeSn channel pMOSFETs compared with Ge control is due to the biaxial compressive strain in GeSn resulting from epitaxial growth of GeSn thin films on relaxed Ge buffer layers.


IEEE Journal of Selected Topics in Quantum Electronics | 2013

{\rm Ge}_{0.93}{\rm Sn}_{0.07}

Birendra Dutt; Hai Lin; Devanand S. Sukhdeo; Boris M. Vulovic; Suyog Gupta; Donguk Nam; Krishna C. Saraswat; James S. Harris

In this paper, a theoretical analysis of unstrained GeSn alloys as a laser gain medium was performed. Using the empirical pseudopotential method, the band structure of GeSn alloys was simulated and verified against experimental data. This model shows that GeSn becomes direct bandgap with 6.55% Sn concentration. The optical gain of GeSn alloys with 0-10% Sn concentration was calculated with different n-type doping concentrations and injection levels. It is shown theoretically that adding Sn greatly increases the differential gain owing to the reduction of energy between the direct and indirect conduction bands. For a double-heterostructure laser, the model shows that at a cavity loss of 50 cm-1, the minimum threshold current density drops 60 times from Ge to Ge0.9Sn0.1, and the corresponding optimum n-doping concentration of the active layer drops by almost two orders of magnitude. These results indicate that GeSn alloys are good candidates for a Si-compatible laser.


Nano Letters | 2013

pMOSFETs

Suyog Gupta; Robert Chen; Yi-Chiau Huang; Yihwan Kim; Errol Antonio C. Sanchez; James S. Harris; Krishna C. Saraswat

We present a new etch chemistry that enables highly selective dry etching of germanium over its alloy with tin (Ge(1-x)Sn(x)). We address the challenges in synthesis of high-quality, defect-free Ge(1-x)Sn(x) thin films by using Ge virtual substrates as a template for Ge(1-x)Sn(x) epitaxy. The etch process is applied to selectively remove the stress-inducing Ge virtual substrate and achieve strain-free, direct band gap Ge0.92Sn0.08. The semiconductor processing technology presented in this work provides a robust method for fabrication of innovative Ge(1-x)Sn(x) nanostructures whose realization can prove to be challenging, if not impossible, otherwise.


international electron devices meeting | 2012

Theoretical Analysis of GeSn Alloys as a Gain Medium for a Si-Compatible Laser

Dennis Lin; AliReza Alian; Suyog Gupta; Bin Yang; Erik Bury; Sonja Sioncke; Robin Degraeve; M. L. Toledano; Raymond Krom; Paola Favia; Hugo Bender; Matty Caymax; Krishna C. Saraswat; Nadine Collaert; Aaron Thean

High-Mobility n-MOSFET options with Ge and InGaAs channels are of intense interests. As the well-known interfacial trap (Dit) problem appears now contained, new challenges are emerging from above the interface. The evidence of oxide border traps (BT) in high-k dielectrics and its effect on the on-state performance of Ge and InGaAs n-MOSFETs are presented in this study through combined trap and transport analyses. The impact of the oxide traps on device frequency response and threshold voltage (Vth) stability could challenge the commercial realization of the high mobility channel MOSFET.


international electron devices meeting | 2012

Highly Selective Dry Etching of Germanium over Germanium–Tin (Ge1–xSnx): A Novel Route for Ge1–xSnx Nanostructure Fabrication

Suyog Gupta; Benjamin Vincent; Bin Yang; Dennis Lin; Federica Gencarelli; J.-Y. Jason Lin; Robert Chen; Olivier Richard; Hugo Bender; Blanka Magyari-Köpe; Matty Caymax; J Dekoster; Yoshio Nishi; Krishna C. Saraswat

We present a detailed theoretical analysis to motivate GeSn for CMOS logic. High quality GeSn films have been obtained on Ge-on-Si using a CVD process. A novel surface passivation scheme is presented to achieve record low trap densities at high-κ/GeSn interface. Using the novel surface passivation method, combined with a low thermal budget device fabrication process, n-channel MOSFETs on GeSn with channel Sn content as high as 8.5% have been demonstrated for the first time.


IEEE Electron Device Letters | 2012

Beyond interface: The impact of oxide border traps on InGaAs and Ge n-MOSFETs

Ashish Pal; Aneesh Nainani; Suyog Gupta; Krishna C. Saraswat

We propose a novel one-transistor (1T) quantum well (QW) DRAM with raised GaP source/drain. This novel device structure shows much better retention time and sense margin than the existing silicon 1T DRAM (with and without QW). Detailed simulation study indicates that the proposed structure is scalable up to 15-nm gate length. The proposed device utilizes nearly lattice-matched heterostructures which have already been realized in the literature.

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