Swapnil Bahl

A Sharable Built-in Self-repair for Semiconductor Memories with 2-D Redundancy Scheme

Newer technologies like 90 nm and 65 nm bring with them new challenges: longer time to process maturity, higher defect densities and poorer yields. The quality of test and repair determines the designs final yield and profitability. With increasing amount of memory on the chip, the need for an efficient and fast converging perfect algorithm for memory repair is increasing becoming important. In this paper, a perfect algorithm is presented for standalone repairable memories as well as for situations where redundancy is shared between different memories. The proposed BISR is composed of Built-in self-test (BIST) and built-in redundancy analysis (BIRA) module. The BISR module has a low overhead - about 5.05 % of memories area for a typical automotive chip. The proper redundancy scheme and the proposed BIRA algorithm ensure a high repair rate for the SOC and shorter test times as well as optimized area and maximum performance.

Self-Programmable Shared BIST for Testing Multiple Memories

Hundreds of memory instances and their frequency of operation have ruled out the possibility of sharing test structures amongst the embedded memories. This paper discusses the techniques and flow for sharing an embedded memory BIST for the at- speed testing of multiple memories on a typical SoC.

State of the art low capture power methodology

Power consumption during test can be significantly higher than during normal functional mode. This paper presents a low power Automated Test Pattern Generation (ATPG) flow for managing capture power in todays power critical designs. It introduces a novel method for sequentially enabling the on-chip clock controllers to generate accurate low power ATPG patterns respecting the power specifications of the design. The effectiveness of the method is demonstrated on several industrial designs that show up power issues during test mode.

A novel method for silicon configurable test flow and algorithms for testing, debugging and characterizing different types of embedded memories through a shared controller

In present day system-on-chips (SOC), a large part (/spl sim/70%) is occupied by memories. The overall yield of the SoC relies heavily on the memory yield. To minimize the test and diagnosis effort, we present a system for silicon configurable test flow and algorithms for different types of memories including multi-port memories, through a shared controller. It supports manufacturing tests as well as diagnosis and electrical AC characterisation of memories. With low area overhead, the proposed microcode based configurable controller gives the test engineer freedom to do complete testing on-chip with few micro-codes.

Power Aware Shift and Capture ATPG Methodology for Low Power Designs

Power management has emerged as a major design objective, both in functional and test mode, in most of the application domains that employ digital ICs. This paper presents a low power ATPG methodology for managing power both in shift and capture mode. The technique exploits the embedded clock gates and provides a good tradeoff between pattern count and reduction in switching activity without any significant coverage loss. The methodology also presents a novel method of selective scan chain reordering for scan compressed designs to reduce shift switching activity with minimal design flow constraints.

EDA solutions to new-defect detection in advanced process technologies

For decades, EDA test generation tools for digital logic have relied on the Stuck-At fault model, despite the fact that process technologies moved forward from TTL (for which the Stuck-At fault model was originally developed) to nanometer-scale CMOS. Under pressure from their customers, especially in quality-sensitive application domains such as automotive, in recent years EDA tools have made great progress in improving their detection capabilities for new defects in advanced process technologies. For this Hot-Topic Session, we invited the three major EDA vendors to present their recent greatest innovations in hiqh-quality automatic test pattern generation, as well as their lead customers to testify of actual production results.

Unifying scan compression

STMicroelectronics has been using scan compression for many years. With the vast variety of designs and the size of the company it is important to deploy an easy to use solution that works for all the conditions. Today we support many different compression schemes DFTMAX, DFTMAX Xtol, Serializer. Each of these solutions is strong in a segment of the designs. DFTMAX Ultra has a technology that provides a single solution for all needs. In this paper we discuss the variety of design scenarios seen in ST from the point of scan compression. Results of DFTMAX Ultra are then presented to show that it is a viable unified solution.

Low Power Test

The power consumed during test mode is higher than the functional mode and becomes significantly higher for low power devices. The increased heat can result in chip burnouts and reliability issues due to electro-migration. This poster presents the reasons for higher power consumption, its consequences, and various solutions, both at hardware and software level, for reducing the overall test mode power. It also highlights the benefits, costs and practicability by applying it on few ST SoCs.