Amit Chhabra

A 3 GHz Dual Core Processor ARM Cortex TM -A9 in 28 nm UTBB FD-SOI CMOS With Ultra-Wide Voltage Range and Energy Efficiency Optimization

This paper presents the implementation details and silicon results of a 3 GHz dual-core ARM Cortex TM -A9 (A9) manufactured in the 28 nm planar Ultra-Thin Box and Body Fully-Depleted CMOS (UTBB FD-SOI) technology. The implementation is based on a fully synthesizable standard design flow. The design exploits the important flexibility provided by the FD-SOI technology, notably a wide Dynamic Voltage and Frequency Scaling (DVFS) range, from 0.52 V to 1.37 V, and Forward Body Bias (FBB) techniques up to 1.3 V. Detailed explanations of the body-biasing techniques specific to this technology are largely presented, in the context of a multi- VT co-integration, which enable this energy efficient silicon implementation. The system integrates all the advanced IPs for energy efficiency as well as the body bias generator and a fast (μs range) dynamic body bias management capability. The measured dual core CPU maximum operation frequency is 3 GHz (for 1.37 V) and it can be operated down to 300 MHz (for 0.52 V) in full continuous DVFS. The obtained relative performance, with respect to an equivalent planar 28 nm bulk CMOS chip, shows an improvement of +237% at 0.6 V, or +544% at 0.61 V with 1.3 V FBB.

FALPEM: Framework for Architectural-Level Power Estimation and Optimization for Large Memory Sub-Systems

Framework is developed for estimation of power at pre register transfer level (RTL) stage for structured memory sub-systems. Power estimation model is proposed specifically targeting power consumed by clock network and interconnect. The model is validated with VCD-based simulation on back-annotated netlist of an 8 MB memory sub-system used as video RAM (VRAM) for high-end graphics applications. This methodology also forms the basis for low-power exploration driving floor plan choice, gating structure of data, and clock network. We demonstrate 57% reduction in dynamic power by using low-power techniques for the 8 MB VRAM used as frame buffer in a graphics processor. FALPEM can be extended to other applications like processor cache and ASIC designs.

Low-Energy Power-ON-Reset Circuit for Dual Supply SRAM

Design of a low-energy power-ON reset (POR) circuit is proposed to reduce the energy consumed by the stable supply of the dual supply static random access memory (SRAM), as the other supply is ramping up. The proposed POR circuit, when embedded inside dual supply SRAM, removes its ramp-up constraints related to voltage sequencing and pin states. The circuit consumes negligible energy during ramp-up, does not consume dynamic power during operations, and includes hysteresis to improve noise immunity against voltage fluctuations on the power supply. The POR circuit, designed in the 40-nm CMOS technology within 10.6-μm2 area, enabled 27× reduction in the energy consumed by the SRAM array supply during periphery power-up in typical conditions.

Temperature-based adaptive memory sub-system in 28nm UTBB FDSOI

Temperature plays a crucial role in deciding SRAM performance especially at very low voltage. SRAM bitcell has conflicting constraints of write-ability and stability at cold (−40°C typically) and hot temperature (125°C typically) respectively. In order to reduce SRAM minimum operating voltage (VMIN), write and stability assist schemes are deployed. Fully-Depleted SOI (FDSOI) technology offers single P-well SRAM bitcell, where a single voltage can be used to adjust the state of the body (or P-well) of all bitcell devices. This voltage can vary from −1.1V to +1.1V. In this paper, we present detailed architecture and implementation of the low-power adaptive memory sub-system that modulates body bias voltage based on the junction temperature to reduce SRAM VMIN. The body is biased to positive voltages up to +1.1V to boost write-ability at cold temperatures and up to −1.1V to boost stability at hot temperatures. In addition, the system selects appropriate assist scheme based on temperature information. We present the dynamic simulation based functional verification environment using temperature and voltage-aware memory models that are compliant with IEEE 1801. We gained 50mV in SRAM VMIN thereby allowing 0.55V operation using high density 0.120μm2 single P-well bitcell in 28nm planar Ultra-Thin Box and Body (UTBB) FDSOI CMOS technology. We also gained 18% dynamic power during regular temperature range of 10°C and 75°C. In addition, due to forward body bias at cold temperature, we gained 30% in SRAM access time.