Syed Ahmed Aamir

Frequency compensation of high-speed, low-voltage CMOS multistage amplifiers

This paper presents the frequency compensation of high-speed, low-voltage multistage amplifiers. Two frequency compensation techniques, the Nested Miller Compensation with Nulling Resistors (NMCNR) and Reversed Nested Indirect Compensation (RNIC), are discussed and employed on two multistage amplifier architectures. A four-stage pseudo-differential amplifier with CMFF and CMFB is designed in a 1.2 V, 65-nm CMOS process. With NMCNR, it achieves a phase margin (PM) of 59° with a DC gain of 75 dB and unity-gain frequency (fug) of 712 MHz. With RNIC, the same four-stage amplifier achieves a phase margin of 84°, DC gain of 76 dB and fug of 2 GHz. Further, a three-stage single-ended amplifier is designed in a 1.1-V, 40-nm CMOS process. The three-stage OTA with RNIC achieves PM of 81°, DC gain of 80 dB and fug of 770 MHz. The same OTA achieves PM of 59° with NMCNR, while maintaining a DC gain of 75 dB and fug of 262 MHz. Pole-splitting, to achieve increased stability, is illustrated for both compensation schemes. Simulations illustrate that the RNIC scheme achieves much higher PM and fug for lower values of compensation capacitance compared to NMCNR, despite the growing number of low voltage amplifier stages.

1.2-V Analog Interface for a 300-MSps HD Video Digitizer in Core 65-nm CMOS

This paper describes the front-end of a fully integrated analog interface for 300 MSps, high-definition video digitizers in a system on-chip environment. The analog interface is implemented in a 1.2 V, 65-nm digital CMOS process and the design minimizes the number of power domains using core transistors only. Each analog video receiver channel contains an integrated multiplexer with a current-mode dc-clamp, a programmable gain amplifier (PGA) and a pseudo second-order RC low-pass filter. The digital charge-pump clamp is integrated with low-voltage bootstrapped tee-switches inside the multiplexer, while restoring the dc component of ac-coupled inputs. The PGA contains a four-stage fully symmetric pseudo-differential amplifier with common-mode feedforward and inherent common-mode feedback, utilized in a closed loop capacitive feedback configuration. The amplifier features offset cancellation during the horizontal blanking. The video interface is evaluated using a unique test signal over a range of video formats for INL+/DNL+, INL-/DNL-. The 0.07-0.39 mV INL, 2-70 μV DNL, and 66-74 dB of SFDR, enable us to target various formats for 9-12 bit Low-voltage digitizers.

A highly tunable 65-nm CMOS LIF neuron for a large scale neuromorphic system

We present the design and measurement of a continuous-time, accelerated, reconfigurable Leaky Integrate and Fire (LIF) neuron model emulated in 65-nm CMOS technology. The neuron circuit is designed as a sub-circuit of our highly integrated neuromorphic prototype chip, the “HICANN-DLS”. The design is geared towards testability and debug features, as well as area and power efficiency. Each neuron in the array integrates current from a multitude of input synapses onto an RC integrator within the synaptic input sub-circuit, where a variable resistor tunes the synaptic time constant. Linear transconductors convert voltage into an equivalent current as well as modeling the leak term, while a pulse generator circuit evokes a digital spike event. Our measurements show that the neuron successfully integrates input synaptic events ranging from a few nA to greater than 10 µA and tunes a wide range of tunable synaptic and membrane time constants. A higher membrane dynamic range of up to 1100 mV, and longer refractory times can be achieved, operating 1000 times faster than biological real-time. The design of the neuron simplifies calibration and reduces the mismatch, as multiple die measurements indicate. We demonstrate a one-to-one correspondence to software simulation for a typical computational model neuron. Due to the wide tunable range, the neuron is to be our general-purpose element of our second generation flexible neuromorphic platform for a variety of computational models.

Neuromorphic circuits for Short-Term Plasticity with recovery control

We present real-time neuromorphic VLSI circuits that implement the synaptic dynamics of Short Term Plasticity (STP). STP supports useful signal processing computational primitives such as change detection and gain control. Compact circuits implementing these mechanisms play a key role in providing neuromorphic VLSI systems with autonomous adaptation capabilities. We propose two different, flexible, short-term adaptation CMOS circuits for controlling the efficacy of synapses in response to incoming spikes. These circuits can be configured to either implement short-term depression or facilitation, with independent control over the adaptation and recovery rates. Our results demonstrate the dynamic properties of the proposed circuits and their behaviour in the frequency domain.

A 1.2-V pseudo-differential OTA with common-mode feedforward in 65-NM CMOS

In this work, we describe the implementation of a 1.2-V pseudo-differential operational transconductance amplifier (OTA) with common-mode feedforward (CMFF) and inherent common-mode feedback (CMFB) in a 65-nm, digital CMOS process. The OTA architecture provides an inherent CMFB when cascaded OTA structures are utilized and this work has studied a cascaded amplifier consisting of four stages. Due to the low-gain using core 65-nm circuit devices, the overall gain must be distributed on all four stages to acquire a gain of more than 60 dB, while maintaining a −3-dB bandwidth of 200 MHz. To achieve high gain, we propose using a modified, positive-feedback, cross-coupled input differential stage. The modified OTA achieves a high output swing of ±0.85 V due to only two stacked transistors, 88 dB DC gain and a third-order harmonic of −60 dB for 800 mV pp at 30 MHz. Further on, in a capacitive buffer configuration, we achieve a high slew rate of 1240 V/µs, −3-dB bandwidth of 509 MHz, signal-to-noise ratio of 63 dB while consuming 10.4 mW power.

A 500-MHz low-voltage programmable gain amplifier for HD video in 65-nm CMOS

This work describes the implementation of a 1.2-V programmable gain amplifier (PGA) for high-definition (HD) video digitizers in a 65-nm digital CMOS process.

A 1.1-V Analog Multiplexer With an Adaptive Digital Clamp for CMOS Video Digitizers

We present the design of an integrated multiplexer and a dc clamp for the input analog interface of a high-speed video digitizer in the 1.1-V 65-nm complementary metal-oxide-semiconductor process. The ac-coupled video signal is dc restored using a novel all-digital current-mode charge pump. An eight-input multiplexer is realized with T-switches, each containing two series-connected bootstrapped switches. A T-switchs grounding branch is merged with the pull-down end of the clamping charge pump. An adaptive digital feedback loop encompassing a video analog-to-digital converter (ADC) controls the clamp charge pump. The bootstrapped switches have been adapted to suit the video environment, allowing on-the-fly recharging. The varying on-resistance of the conventional bootstrapped switch is utilized to linearize the multiplexer response by canceling the effect of the nonlinear load capacitance contributed by the clamp transistors. Under worst case conditions, the multiplexer maintains a 62-85-dB spurious-free dynamic range over a range of known input video frequencies, and it reduces the second-order harmonic component upon optimization. The dc clamp provides 12-bit precision over the full range of the video ADC and can set the dc at the target level for at most 194 video lines.