Jacob Wikner

Modeling of CMOS digital-to-analog converters for telecommunication

This paper gives an overview of some of the effects caused by circuit mismatch and parasitics in binary weighted digital-to-analog converters (DACs), and, as a special case, a current-steering CMOS converter. Matlab is used as a behavior-level simulator. In telecommunications applications, the frequency-domain parameters are of the greatest importance. Therefore, the characterization of the device and its performance is determined by frequency parameters such as the signal-to-noise ratio, spurious-free dynamic range, multitone power ratio, etc. In this paper, we show how these frequency-domain parameters are affected when mismatch errors and finite output impedance are applied to a current-steering CMOS DAC. We discuss how static performance is affected when changing the size of the errors and fundamental circuit parameters. The impact of dynamic errors such as glitches, slewing, and bit skew is discussed. Measurement results from 14-bit DACs are also shown to illustrate the correlation with the modeling.

Modelling of CMOS digital-to-analog converters for telecommunication

In telecommunication applications the digital-to-analog converter is a crucial building block. For this kind of application dynamic performance, rather than static performance, is of the greatest importance. This paper discusses the aspects of the dynamic performance of digital-to-analog converters and models the influence of non-ideal components (such as output impedance, mismatch, circuit noise, etc.) on the dynamic performance. The purpose of this modelling is to provide a design guidance for high dynamic performance digital-to-analog converters.

Dynamic element matching in D/A converters with restricted scrambling

Inaccurate matching of the analog sources in a D/A converter causes a signal-dependent error in the output. This distortion can be transformed into noise by assigning the digital control to the analog sources randomly, which is a technique referred to as dynamic element matching. In this paper, we present a dynamic element matching technique where the scrambling is restricted such that the glitches in the converter are minimized. By this, both the distortion due to glitches is reduced, and the signal-dependent error due to matching is suppressed. A hardware structure is proposed that implements the approach, and the operation of the hardware is described. Simulation results indicate that the method has a potential of yielding as good reduction of glitches as the optimal thermometer-coded converter and a signal-dependent error level that is almost as low as achieved with prior dynamic element matching techniques.

Influence of Circuit Imperfections on the Performance of DACs

Digital-to-analog converters are crucial building blocks for telecommunication applications. For this kind of applications, the traditional static performance requirements do not apply. The dynamic performance is of the greatest importance. This paper discusses the aspects of the performance of CMOS digital-to-analog converters and models the influence of non-idealities of circuit components (such as output impedance, mismatch, circuit noise, etc.) on the frequency-domain performance. Both deterministic and stochastic effects are modeled. The purpose of this modeling is to provide an insightful design guide for high dynamic performance CMOS digital-to-analog converters.

A CMOS digital-to-analog converter chipset for telecommunication

Describes a DAC chipset developed specifically for telecommunication applications. The DAC chipset is implemented in Ericssons in-house 0.6-micron CMOS process and operates on a supply voltage ranging from 1.5 V to 5 V with the number of bits ranging from 10 to 14 bits, and data rate from 50 Msamples/s@1.5 V to over 100 Msamples/s@5 V.

Characterization of a CMOS current-steering DAC using state-space models

Performance limitations on current-steering digital-to-analog converters (DACs) are due to finite output impedances, nonideal switches, parasitic capacitances, matching, etc. In this work we present a dynamic state-space model of a 14-bit current-steering DAC which includes dynamic nonidealities. Simulation results are presented and compared to measurement results. The model can be used for fast performance estimation of D/A converters.

Frequency compensation of high-speed, low-voltage CMOS multistage amplifiers

This paper presents the frequency compensation of high-speed, low-voltage multistage amplifiers. Two frequency compensation techniques, the Nested Miller Compensation with Nulling Resistors (NMCNR) and Reversed Nested Indirect Compensation (RNIC), are discussed and employed on two multistage amplifier architectures. A four-stage pseudo-differential amplifier with CMFF and CMFB is designed in a 1.2 V, 65-nm CMOS process. With NMCNR, it achieves a phase margin (PM) of 59° with a DC gain of 75 dB and unity-gain frequency (fug) of 712 MHz. With RNIC, the same four-stage amplifier achieves a phase margin of 84°, DC gain of 76 dB and fug of 2 GHz. Further, a three-stage single-ended amplifier is designed in a 1.1-V, 40-nm CMOS process. The three-stage OTA with RNIC achieves PM of 81°, DC gain of 80 dB and fug of 770 MHz. The same OTA achieves PM of 59° with NMCNR, while maintaining a DC gain of 75 dB and fug of 262 MHz. Pole-splitting, to achieve increased stability, is illustrated for both compensation schemes. Simulations illustrate that the RNIC scheme achieves much higher PM and fug for lower values of compensation capacitance compared to NMCNR, despite the growing number of low voltage amplifier stages.

D/A conversion with linear-coded weights

In design of high-speed, high resolution D/A converters, glitches in the output are of major concern. To tradeoff between hardware complexity and glitch performance the current practice is to use a hybrid converter where the most significant bits are thermometer coded and the least significant bits are binary-scaled. As an alternative to this scheme, we propose a new method for D/A conversion based on linear coding of the weights (1, 2, 3,...). The new method improves the glitch performance and reduces the hardware complexity for high resolution converters. An algorithm for converting the digital binary-coded input word into a digital word controlling the linear weights is given. In an example, the linear-coded weights are applied to a current-steering D/A converter. We discuss properties such as layout properties, device matching, and mixed-signal issues.

Glitch minimization and dynamic element matching in D/A converters

In this paper we present a novel method for combining thermometer coding and dynamic element matching (DEM) in a digital-to-analog converter (DAC). The proposed method combines DEM with a minimization of glitch power. The glitch power may in a DEM solution make a significant contribution to the total noise power. The switch based solution provides a structural solution where it is possible to implement parts of the method, which reduce the area required for implementation.

Spectral shaping of DAC nonlinearity errors through modulation of expected errors

Traditionally, delta-sigma modulation has been used for shaping of quantization noise. We present a modified version of delta-sigma modulation which also takes into account unwanted nonlinearities by feeding back not only the quantization error, but also the expected physical error. Behavioral-level simulations of a 5th-order structure showing an improvement of up to 4 effective bits are included.