Syed Mahfuzul Aziz

Review of Cyber-Physical System in Healthcare

Cyber-physical system (CPS) is an integration of physical processes with computation and communication. It has the ability to add more intelligence to social life. Wireless sensor networks (WSN) can be a vital part of CPS as strong sensing capability is one of the major driving factors for CPS applications. CPS is still considered to be a nascent technology, and there are many challenges yet to be addressed. A few CPS applications in healthcare have been proposed to date, and they lack the flexibility of technology integration, such as integration of computing resources with sensor networks. This paper presents a survey of CPS in healthcare applications that have been proposed to date by academia as well as industry. A comprehensive taxonomy is also provided that characterizes and classifies different components and methods that are required for the application of CPS in healthcare. The taxonomy not only highlights the similarities and differences of the state-of-the-art technologies utilized in CPS for healthcare from the perspective of WSN and Cloud Computing but also identifies the areas that require further research. It is expected that this taxonomy and its mapping to relevant systems will be highly useful for further development of CPS for healthcare.

Energy Efficient Image Transmission in Wireless Multimedia Sensor Networks

The key obstacle to communicating images over wireless sensor networks has been the lack of suitable processing architecture and communication strategies to deal with the large volume of data. High packet error rates and the need for retransmission make it inefficient in terms of energy and bandwidth. This paper presents novel architecture and protocol for energy efficient image processing and communication over wireless sensor networks. Practical results show the effectiveness of these approaches to make image communication over wireless sensor networks feasible, reliable and efficient.

FPGA Implementation of a LDPC Decoder using a Reduced Complexity Message Passing Algorithm

In this paper, a simplified message passing algorithm for decoding Low-Density Parity-Check (LDPC) codes is proposed with a view to reduce the implementation complexity. The algorithm is based on simple hard-decision decoding techniques while utilizing the advantages of soft channel information to improve decoder performance. It has been validated through simulation using LDPC code compliant with Wireless Local Area Network (WLAN – IEEE 802.11n) standard. The results show that theproposed algorithm can achieve significant improvement in bit error rate (BER) performance and average decoding iterations compared to fully hard-decision based decoding algorithms. The proposed algorithm has been implemented and tested on Xilinx Virtex 5 FPGA. With significantly reduced hardware resources, the implemented decoder can achieve an average throughput of ~16.2 Gbps with a BER performance of 10-5 at an Eb/No of 6.25 dB.

Sensor Anomaly Detection in Wireless Sensor Networks for Healthcare

Wireless Sensor Networks (WSN) are vulnerable to various sensor faults and faulty measurements. This vulnerability hinders efficient and timely response in various WSN applications, such as healthcare. For example, faulty measurements can create false alarms which may require unnecessary intervention from healthcare personnel. Therefore, an approach to differentiate between real medical conditions and false alarms will improve remote patient monitoring systems and quality of healthcare service afforded by WSN. In this paper, a novel approach is proposed to detect sensor anomaly by analyzing collected physiological data from medical sensors. The objective of this method is to effectively distinguish false alarms from true alarms. It predicts a sensor value from historic values and compares it with the actual sensed value for a particular instance. The difference is compared against a threshold value, which is dynamically adjusted, to ascertain whether the sensor value is anomalous. The proposed approach has been applied to real healthcare datasets and compared with existing approaches. Experimental results demonstrate the effectiveness of the proposed system, providing high Detection Rate (DR) and low False Positive Rate (FPR).

Object extraction scheme and protocol for energy efficient image communication over wireless sensor networks

To date, wireless sensor networks lack the most powerful human sense - vision. This is largely due to two main problems: (1) available wireless sensor nodes lack the processing capability and energy resource required to efficiently process and communicate large volume of image data and (2) the available protocols do not provide the queue control and error detection capabilities required to reduce packet error rate and retransmissions to a level suitable for wireless sensor networks. This paper presents an innovative architecture for object extraction and a robust application-layer protocol for energy efficient image communication over wireless sensor networks. The protocol incorporates packet queue control mechanism with built-in CRC to reduce packet error rate and thereby increase data throughput. Unlike other image transmission protocols, the proposed protocol offers flexibility to adjust the image packet size based on link conditions. The proposed processing architecture achieves high speed object extraction with minimum hardware requirement and low power consumption. The system was successfully designed and implemented on FPGA. Experimental results obtained from a network of sensor nodes utilizing the proposed architecture and the application-layer protocol reveal that this novel approach is suitable for effectively communicating multimedia data over wireless sensor networks.

Efficient parallel architecture for multi-level forward discrete wavelet transform processors

A resource efficient and high-performance architecture for a two-dimensional multi-level discrete wavelet transform processor is presented in this paper. The JPEG2000 standard integer lossless 5-3 filter has been implemented. It achieves optimal hardware utilisation with minimal combinational logic block slices and high frequency of operation. To reduce the hardware complexity and to achieve high performance the proposed architecture implements lifting scheme with a single multiplier-free processing element to perform both predict and update operations. Symmetric extension is used at image boundaries without requiring any extra clock cycle. The generic architecture is very flexible and can perform up to five levels of forward transform on any arbitrary image size. Synthesis of the 5-level architecture on Xilinx Virtex 5 FPGA shows that the processor can achieve a maximum frequency of operation of 221.44MHz. The reduced hardware complexity and high frequency of operation render the design suitable for incorporation in image processing applications requiring fast operations. The 5-level design has been successfully implemented on a Xilinx Spartan 3E FPGA, utilising only 1104 slices for a 512-by-512 pixel test image, the lowest hardware requirements for a 5-level discrete wavelet transform processor reported to date.

An area efficient LDPC decoder using a reduced complexity min-sum algorithm

Hardware implementation of Low-Density Parity-Check (LDPC) decoders using conventional algorithms such as Sum-Product or Min-Sum requires large amount of hardware resources. A rather simplistic way to reduce hardware resources is to reduce the intrinsic message quantization. However this adversely affects the bit error rate (BER) performance significantly. In this paper, a resource efficient LDPC decoder based on a reduced complexity Min-Sum algorithm is presented. It reduces the inter-connect complexity by restricting the extrinsic message length to 2 bits and also simplifies the check node operation. Simulation at the algorithmic level shows that the proposed decoder achieves BER performance better than that of a 3-bit Min-Sum decoder, and therefore addresses the problem of massive BER performance degradation of a 2-bit Min-Sum decoder. The reduction in algorithmic complexity and further hardware optimization of the variable node leads to significant savings in hardware resources compared to 3-bit Min-Sum. An LDPC decoder with a code length of 1152 bits has been implemented on a Xilinx FPGA using the proposed algorithmic and hardware enhancements. With a 0.1dB BER performance gain to that of 3-bit Min-Sum decoder, the proposed decoder saves about 18% of FPGA slices and provides a higher throughput.

FPGA Implementation of High Performance LDPC Decoder Using Modified 2-Bit Min-Sum Algorithm

In this paper, a reduced complexity Low-Density Parity-Check (LDPC) decoder is designed and implemented on FPGA using a modified 2-bit Min-Sum algorithm. Simulation results reveal that the proposed decoder has improvement of 1.5 dB Eb/No at 10-5 bit error rate (BER) and requires fewer decoding iterations compared to original 2-bit Min-Sum algorithm. With a comparable BER performance to that of 3- bit Min-Sum algorithm, the decoder implemented using modified 2-bit Min-Sum algorithm saves about 18% of FPGA slices and can achieve an average throughput of 10.2 Gbps at 4 dB Eb/No.

Effective Teaching of the Physical Design of Integrated Circuits Using Educational Tools

This paper presents the strategies used for effective teaching and skill development in integrated circuit (IC) design using project-based learning (PBL) methodologies. It presents the contexts in which these strategies are applied to IC design courses at the University of South Australia, Adelaide, Australia, and the National Institute of Applied Science (INSA), Toulouse, France. Collaborations among the faculty members of the two institutions have produced a set of learning resources and design tools to support the development of industry-relevant design skills and lifelong learning skills. At the pedagogical level, the emphasis is on the development of practical circuit design, critical thinking, and problem-solving skills rather than the mastery of complex circuit design tools. The courses enable students to learn about the most recent technological developments and their implications, using a set of user-friendly tools. The PBL methodologies, intuitive design tools, and latest technology models have consistently produced high levels of student satisfaction with the overall quality of the courses at the two institutions.

Identification of Foot Pathologies Based on Plantar Pressure Asymmetry

Foot pathologies can negatively influence foot function, consequently impairing gait during daily activity, and severely impacting an individual’s quality of life. These pathologies are often painful and correspond with high or abnormal plantar pressure, which can result in asymmetry in the pressure distribution between the two feet. There is currently no general consensus on the presence of asymmetry in able-bodied gait, and plantar pressure analysis during gait is in dire need of a standardized method to quantify asymmetry. This paper investigates the use of plantar pressure asymmetry for pathological gait diagnosis. The results of this study involving plantar pressure analysis in fifty one participants (31 healthy and 20 with foot pathologies) support the presence of plantar pressure asymmetry in normal gait. A higher level of asymmetry was detected at the majority of the regions in the feet of the pathological population, including statistically significant differences in the plantar pressure asymmetry in two regions of the foot, metatarsophalangeal joint 3 (MPJ3) and the lateral heel. Quantification of plantar pressure asymmetry may prove to be useful for the identification and diagnosis of various foot pathologies.