Vikram Arkalgud Chandrasetty

FPGA Implementation of a LDPC Decoder using a Reduced Complexity Message Passing Algorithm

In this paper, a simplified message passing algorithm for decoding Low-Density Parity-Check (LDPC) codes is proposed with a view to reduce the implementation complexity. The algorithm is based on simple hard-decision decoding techniques while utilizing the advantages of soft channel information to improve decoder performance. It has been validated through simulation using LDPC code compliant with Wireless Local Area Network (WLAN – IEEE 802.11n) standard. The results show that theproposed algorithm can achieve significant improvement in bit error rate (BER) performance and average decoding iterations compared to fully hard-decision based decoding algorithms. The proposed algorithm has been implemented and tested on Xilinx Virtex 5 FPGA. With significantly reduced hardware resources, the implemented decoder can achieve an average throughput of ~16.2 Gbps with a BER performance of 10-5 at an Eb/No of 6.25 dB.

An area efficient LDPC decoder using a reduced complexity min-sum algorithm

Hardware implementation of Low-Density Parity-Check (LDPC) decoders using conventional algorithms such as Sum-Product or Min-Sum requires large amount of hardware resources. A rather simplistic way to reduce hardware resources is to reduce the intrinsic message quantization. However this adversely affects the bit error rate (BER) performance significantly. In this paper, a resource efficient LDPC decoder based on a reduced complexity Min-Sum algorithm is presented. It reduces the inter-connect complexity by restricting the extrinsic message length to 2 bits and also simplifies the check node operation. Simulation at the algorithmic level shows that the proposed decoder achieves BER performance better than that of a 3-bit Min-Sum decoder, and therefore addresses the problem of massive BER performance degradation of a 2-bit Min-Sum decoder. The reduction in algorithmic complexity and further hardware optimization of the variable node leads to significant savings in hardware resources compared to 3-bit Min-Sum. An LDPC decoder with a code length of 1152 bits has been implemented on a Xilinx FPGA using the proposed algorithmic and hardware enhancements. With a 0.1dB BER performance gain to that of 3-bit Min-Sum decoder, the proposed decoder saves about 18% of FPGA slices and provides a higher throughput.

FPGA Implementation of High Performance LDPC Decoder Using Modified 2-Bit Min-Sum Algorithm

In this paper, a reduced complexity Low-Density Parity-Check (LDPC) decoder is designed and implemented on FPGA using a modified 2-bit Min-Sum algorithm. Simulation results reveal that the proposed decoder has improvement of 1.5 dB Eb/No at 10-5 bit error rate (BER) and requires fewer decoding iterations compared to original 2-bit Min-Sum algorithm. With a comparable BER performance to that of 3- bit Min-Sum algorithm, the decoder implemented using modified 2-bit Min-Sum algorithm saves about 18% of FPGA slices and can achieve an average throughput of 10.2 Gbps at 4 dB Eb/No.

A reduced complexity message passing algorithm with improved performance for LDPC decoding

In this paper, a simplified message passing algorithm for decoding Low-Density Parity-Check (LDPC) codes is proposed with a view to reduce the implementation complexity. The algorithm is based on simple hard-decision decoding techniques while utilizing the advantages of soft channel information for improvement in decoder performance. The algorithm has been validated through simulation using LDPC code compliant with Wireless Local Area Network (WLAN -IEEE 802.11n) standard. The results show that the proposed algorithm can achieve significant improvement in bit error rate (BER) performance and average decoding iterations compared to fully hard-decision based decoding algorithms.

A Highly Flexible LDPC Decoder using Hierarchical Quasi-Cyclic Matrix with Layered Permutation

Hardware implementation of partially-parallel Low-Density Parity-Check (LDPC) decoders using unstructured random matrices is very complex and requires huge hardware resources. To alleviate the complexity and minimize resource requirements, structured LDPC matrices are used. This paper presents a novel technique for constructing a multi-level Hierarchical Quasi-Cyclic (HQC) structured matrix for LDPC decoder. A unique multi-level structure of the proposed matrix provides flexibility in generating different code lengths and code rates for various applications such as WiMAX, WLAN and DVB-S2. In addition, different combinations of permuted sub-matrices are inserted in layers at different levels of matrix hierarchy to provide virtual randomness in the LDPC matrix. Simulation results show that the HQC matrices generated using the proposed technique have a marginal loss of less than 0.1 dB at a bit error rate (BER) performance 10 -5 compared to unstructured random matrices. A hardware model of the proposed matrix structure has been developed and synthesized on Xilinx FPGA to verify the flexibility features, hardware requirements and to analyze the performance of the LDPC decoder.

A multi-level Hierarchical Quasi-Cyclic matrix for implementation of flexible partially-parallel LDPC decoders

A novel technique for constructing a multi-level Hierarchical Quasi-Cyclic (HQC) matrix for Low-Density Parity-Check (LDPC) decoder is presented in this paper. A unique multi-level structure of the proposed matrix provides flexibility in generating different code lengths and code rates for various applications such as WiMax, WLAN and DVB-S2. In addition, different combinations of permuted random sub-matrices are embedded in layers, to provide virtual randomness in the LDPC matrix. Simulation results show that the HQC matrices generated by using the proposed technique has bit error rate (BER) performance very close to that of unstructured random matrices. A prototype model of partially-parallel decoder architecture has been designed by using the various matrix configurations available in the proposed technique. FPGA design results show that the proposed decoder is resource efficient and the power requirements are comparable to that of ASIC based decoders.

Analysis of performance and implementation complexity of simplified algorithms for decoding Low-Density Parity-Check codes

This paper presents a novel technique to significantly reduce the implementation complexity of Low-Density Parity-Check (LDPC) decoders. The proposed technique uses high precision soft messages at the variable nodes but scales down the extrinsic message length, which reduces the number of interconnections between variable and check nodes. It also simplifies the check node operation. The effect on performance and complexity of the decoders due to such simplification is analyzed. A prototype model of the proposed decoders compliant with the WiMax application standard has been implemented and tested on Xilinx Virtex 5 FPGA. The implementation results show that the proposed decoders can achieve significant reduction in hardware complexity with comparable decoding performance to that of Min-Sum algorithm based decoders. The proposed decoders are estimated to achieve an average throughput in the range of 6–11 Gbps, even with short code lengths.

CMOS Digital Design

The demand for electronic and multimedia devices is increasing exponentially. This demand in-turn has propelled the need for memory chips to process instructions, store data and other multimedia content. Some of the most common memory structures used for faster data and program memory access are Static (SRAM) and Dynamic (DRAM) memory.

Construction of a multi-level Hierarchical Quasi-Cyclic matrix with layered permutation for partially-parallel LDPC decoders

Implementation of partially-parallel (Low-Density Parity-Check) LDPC decoders using unstructured random matrices is very complex and requires huge hardware resources. To alleviate the complexity and minimize resource requirements, structured LDPC matrices are used. This paper presents a novel technique for constructing a multi-level Hierarchical Quasi-Cyclic (HQC) structured matrix for LDPC decoders. A unique multi-level structure of the proposed matrix provides flexibility in generating different code lengths and code rates for various applications such as WiMAX, WLAN and DVB-S2. In addition, different combinations of permuted sub-matrices are inserted in layers, to provide virtual randomness in the LDPC matrix. Simulations results show that the HQC matrices generated using the proposed technique have a marginal loss of less than 0.1 dB at a bit error rate (BER) performance of 10−5, compared to unstructured random matrices. The proposed matrix therefore provides BER performance close to random matrices while significantly reducing hardware resource requirements.

Resource efficient LDPC decoders for multimedia communication

Achieving high image quality is an important aspect in an increasing number of wireless multimedia applications. These applications require resource efficient error correction hardware to detect and correct errors introduced by the communication channel. This paper presents an innovative flexible architecture for error correction using Low-Density Parity-Check (LDPC) codes. The proposed partially-parallel decoder architecture utilizes a novel code construction technique based on multi-level Hierarchical Quasi-Cyclic (HQC) matrix. The proposed architecture is resource efficient, provides scalable throughput and requires substantially less power compared to other decoders reported to date. The proposed decoder has been implemented on a Xilinx FPGA suitable for WiMAX application and achieves a throughput of 548Mbps. Performance evaluation of the decoder has been carried out by transmitting JPEG images over a wireless noisy channel and comparing the quality of the reconstructed images with those from other similar decoders.