Sying-Jyan Wang

Design and synthesis of self-checking VLSI circuits

Self-checking circuits can detect the presence of both transient and permanent faults. A self-checking circuit consists of a functional circuit that produces encoded output vectors and a checker that checks the output vectors. The checker has the ability to expose its own faults as well. The functional circuit can be either combinational or sequential. A self-checking system consists of an interconnection of self-checking circuits. The advantage of such a system is that errors can be caught as soon as they occur; thus, data contamination is prevented. Methods for the cost-effective design of combinational and sequential self-checking functional circuits and checkers are examined. The area overhead for all proposed design alternatives is studied in detail. >

Algorithm-based fault tolerance for FFT networks

Algorithm-based fault tolerance (ABFT) is a low-overhead system-level fault tolerance technique. Many ABFT schemes have been proposed in the past for fast Fourier transform (FFT) networks. In this paper, a new ABFT scheme for FFT networks is proposed. We show that the new approach maintains the high throughput of previous schemes, yet needs lower hardware overhead and achieves higher fault converge than previous schemes by J.Y. Jou et al. (1988) and D.I. Tao et al. (1990). >

Test and diagnosis of faulty logic blocks in FPGAs

Since Field programmable gate arrays (FPGAs) are reprogrammable, faults in them can be easily tolerated once fault sites are located. In this paper we present a method for the testing and diagnosis of faults in FPGAs. The proposed method imposes no hardware overhead, and requires minimal support from external test equipments. Test time depends only on the number of faults, and is independent of the chip size. With the help of this technique, chips with faults can still be used. As a result, the chip yield can be improved and chip cost is reduced. Experimental results are given to show the feasibility of this method.

Low power parallel multiplier with column bypassing

Power management has become a great concern in VLSI design in recent years. In this paper, we present a low power parallel multiplier design, in which some columns in the multiplier array can be turned-off whenever their outputs are known. In this case, the columns are bypassed, and thus the switching power is saved. The advantage of this design is that it maintains the original array structure without introducing extra boundary cells, as did previous designs. Experimental results show that it saves 10% power for random inputs. Higher power reduction can be achieved if the operands contain more 0s than 1s. Compared with row-bypassing multipliers, this approach achieves higher power reduction with smaller area overhead.

Testing and diagnosis of interconnect structures in FPGAs

Since Field Programmable Gate Arrays (FPGAs) are reprogrammable, faults in them can be easily tolerated once fault sites are located. Previous research on diagnosis of FPGAs mainly deal with faulty logic blocks. In this paper we present a method for the testing and diagnosis of faults in the interconnect structures of FPGAs. A predefined set of tests that can locate all single faults and many multiple faults is presented. Other multiple faults can be located with an adaptive test set. This work, combined with previous works on the diagnosis of faulty logic blocks in FPGAs, makes it possible to utilize FPGAs with faults.

Scan-Chain Partition for High Test-Data Compressibility and Low Shift Power Under Routing Constraint

The degree of achievable test-data compression depends on not only the compression scheme but also the structure of the applied test data. Therefore, it is possible to improve the compression rate of a given test set by carefully organizing the way that test data are present in the scan structure. The relationship between signal probability and test-data entropy is explored in this paper, and the results show that the theoretical maximum compression can be increased through a partition of scan flip-flops such that the test data present in each partition have a skewed signal distribution. In essence, this approach simply puts similar scan flip-flops in an adjacent part of a scan chain, which also helps to reduce shift power in the scan test process. Furthermore, it is shown that the intrapartition scan-chain order has little impact on the compressibility of a test set; thus, it is easy to achieve higher test compression with low routing overhead. Experimental results show that the proposed partition method can raise the compression rates of various compression schemes by more than 17%, and the average reduction in shift power is about 50%. In contrast, the increase in routing length is limited.

A reseeding technique for LFSR-based BIST applications

In this paper, we describe a new design methodology for LFSR-based test pattern generators (TPG). Multiple seeds are produced by the TPG itself to deal with hard-to-detect faults, and this function is achieved without using a ROM to store the seeds. A reseeding logic is incorporated in the TPG, which loads new seeds into the LFSR whenever specific states are reached. In this way, useless test vectors are skipped and thus the test application time can be greatly reduced. We experiment the design methodology by applying it to some MCNC benchmark circuits, and the results show that TPGs designed with this technique require much less hardware overhead than the previous known reseeding techniques.

Low-Power BIST With a Smoother and Scan-Chain Reorder Under Optimal Cluster Size

The authors propose a low-power testing methodology for the scan-based built-in self-test. This approach combines a low-power test pattern generator (TPG) with scan-chain reordering to achieve low-power testing without losing fault coverage. Three main issues are addressed. First, a smoother is included in the TPG to reduce the average power consumption. However, the fault coverage may be adversely affected by the smoother; hence, a cluster-based scan-chain reordering is employed to remedy this problem. If a very-large power reduction is necessary, the fault-coverage drop can become significant. This can be addressed by reseeding. The second topic of this paper is to give a detailed analysis on the optimal cluster size to minimize the scan-chain length. Finally, a fast and efficient algorithm is developed for scan-chain reorder in order to improve the fault coverage. The reordering algorithm is very efficient in terms of computation time, and the routing length of the reordered scan chain is comparable to or smaller than the result given by commercial tools. Experimental results show that the proposed method provides a significant and consistent reduction in the average test power, and the fault coverage is similar to previous methods with the same test lengths

Design and synthesis of self-checking VLSI circuits and systems

Self-checking circuits and systems can detect the presence of both transient and permanent faults. The advantage of such a system is that errors can be caught as soon as they occur, and thus data contamination is prevented. Although much effort has been concentrated on the design of self-checking checkers by previous researchers, very few results have been presented for the design of self-checking functional circuits, and fewer still for the design of self-checking systems. Methods are explored for the cost-effective design of combinational and sequential functional circuits, checkers and systems.<<ETX>>

Layout-aware scan chain reorder for launch-off-shift transition test coverage

Launch-off-shift (LOS) is a popular delay test technique for scan-based designs. However, it is usually not possible to achieve good delay fault coverage in LOS test due to conflicts in test vectors. In this article, we propose a layout-based scan chain ordering method to improve fault coverage for LOS test with limited routing overhead. A fast and effective algorithm is used to eliminate conflicts in test vectors while at the same time restrict the extra scan chain routing. This approach provides many advantages. (1) The proposed method can improve delay fault coverage for LOS test. (2) With layout information taken into account, the routing penalty is limited, and thus the impact on circuit performance will not be significant. Experimental results show that the proposed LOS test method achieves about the same level of delay fault coverage as enhanced scan does, while the average scan chain wire length is about 2.2 times of the shortest scan chain.