Sylvie Renaud

Neuromorphic silicon neuron circuits

Hardware implementations of spiking neurons can be extremely useful for a large variety of applications, ranging from high-speed modeling of large-scale neural systems to real-time behaving systems, to bidirectional brain–machine interfaces. The specific circuit solutions used to implement silicon neurons depend on the application requirements. In this paper we describe the most common building blocks and techniques used to implement these circuits, and present an overview of a wide range of neuromorphic silicon neurons, which implement different computational models, ranging from biophysically realistic and conductance-based Hodgkin–Huxley models to bi-dimensional generalized adaptive integrate and fire models. We compare the different design methodologies used for each silicon neuron design described, and demonstrate their features with experimental results, measured from a wide range of fabricated VLSI chips.

Neuromimetic ICs with analog cores: an alternative for simulating spiking neural networks

This paper aims at discussing the implementation of simulation systems for SNN based on analog computation cores (neuromimetic ICs). Such systems are an alternative to completely digital solutions for the simulation of spiking neurons or neural networks. Design principles for the neuromimetic ICs and the hosting systems are presented together with their features and performances. The authors summarize the existing architectures and neuron models used in such systems, when configured as stand-alone tools for simulating ANN or together with a neurophysiology set-up to study hybrid living artificial neural networks. As a primary illustration, the authors present results from one of the platforms: hardware simulations of single neurons and adaptive neural networks modeled using the Hodgkin-Huxley formalism for point neurons and spike-timing dependent plasticity algorithms for the network adaptation. Additional examples are detailed in the other papers of the session.

A

Neuronal variability has been thought to play an important role in the brain. As the variability mainly comes from the uncertainty in biophysical mechanisms, stochastic neuron models have been proposed for studying how neurons compute with noise. However, most papers are limited to simulating stochastic neurons in a digital computer. The speed and the efficiency are thus limited especially when a large neuronal network is of concern. This brief explores the feasibility of simulating the stochastic behavior of biological neurons in a very large scale integrated (VLSI) system, which implements a programmable and configurable Hodgkin-Huxley model. By simply injecting noise to the VLSI neuron, various stochastic behaviors observed in biological neurons are reproduced realistically in VLSI. The noise-induced variability is further shown to enhance the signal modulation of a neuron. These results point toward the development of analog VLSI systems for exploring the stochastic behaviors of biological neuronal networks in large scale.Neuronal variability has been thought to play an important role in the brain. As the variability mainly comes from the uncertainty in biophysical mechanisms, stochastic neuron models have been proposed for studying how neurons compute with noise. However, most papers are limited to simulating stochastic neurons in a digital computer. The speed and the efficiency are thus limited especially when a large neuronal network is of concern. This brief explores the feasibility of simulating the stochastic behavior of biological neurons in a very large scale integrated (VLSI) system, which implements a programmable and configurable Hodgkin-Huxley model. By simply injecting noise to the VLSI neuron, various stochastic behaviors observed in biological neurons are reproduced realistically in VLSI. The noise-induced variability is further shown to enhance the signal modulation of a neuron. These results point toward the development of analog VLSI systems for exploring the stochastic behaviors of biological neuronal networks in large scale.

Q

In this paper, we present a library of analog operators used for the analog real-time computation of the Hodgkin-Huxley formalism. These operators make it possible to design a silicon (Si) neuron that is dynamically tunable, and that reproduces different kinds of neurons. We used an original method in neuromorphic engineering to characterize this Si neuron. In electrophysiology, this method is well known as the “voltage-clamp” technique. We also compare the features of an application-specific integrated circuit built with this library with results obtained from software simulations. We then present the complex behavior of neural membrane voltages and the potential applications of this Si neuron.

-Modification Neuroadaptive Control Architecture for Discrete-Time Systems

The traditional dilemma for performing network simulations with analog circuits is the great difficulty of handling the connectivity in hardware. The main problem is that hardware-based connectivity must be built following predefined plasticity and connectivity rules, and that once the hardware is built, it is usually not possible to change its configuration. We show here an alternative system in which the membrane equations are solved in analog ASIC circuits, but the connectivity remains controlled by a digital computer. We illustrate the behavior of this system by comparing the analog simulations with traditional computer simulations of the same models.

A Library of Analog Operators Based on the Hodgkin-Huxley Formalism for the Design of Tunable, Real-Time, Silicon Neurons

We review different applications of silicon conductance-based neuron models implemented on analog circuits. At the single-cell level, we describe a circuit in which conductances are programmed to simulate various Hodgkin-Huxley type models; integrated in a hardware/software system, they provide a simulation tool; an illustrative example is the simulation of bursting neurons of the thalamus. At the network level, we present a mixed analog-digital architecture, where the connectivity and the plasticity rules are implemented digitally and are therefore very flexible. These circuits provide valuable tools for real-time simulations, including hybrid applications where single-neuron or network models are interfaced with biological cells.

Real-time simulations of networks of Hodgkin-Huxley neurons using analog circuits

This paper presents an analog neuromimetic ASIC. It integrates Hodgkin-Huxley (HH) model types, computed in real-time and in analog continuous mode. We developed a library of sub-circuits calculating the elementary mathematical functions encountered in the HH models. Those sub-circuits are organized to form the model set of equations, in which all numerical parameters are dynamically tunable via a mixed analog-digital interface. Neural activity examples are presented to validate the library elements and illustrate the diversity of models simulated by a single ASIC

Hardware computation of conductance-based neuron models

We propose a new estimation method for the characterization of the Hodgkin-Huxley formalism. This method is an alternative technique to the classical estimation methods associated with voltage clamp measurements. It uses voltage clamp type recordings, but is based on the differential evolution algorithm. The parameters of an ionic channel are estimated simultaneously, such that the usual approximations of classical methods are avoided and all the parameters of the model, including the time constant, can be correctly optimized. In a second step, this new estimation technique is applied to the automated tuning of neuromimetic analog integrated circuits designed by our research group. We present a tuning example of a fast spiking neuron, which reproduces the frequency-current characteristics of the reference data, as well as the membrane voltage behavior. The final goal of this tuning is to interconnect neuromimetic chips as neural networks, with specific cellular properties, for future theoretical studies in neuroscience.

A Conductance-Based Silicon Neuron with Dynamically Tunable Model Parameters

Hybrid living-artificial neural networks are an efficient and adaptable experimental support to explore the dynamics and the adaptation process of biological neural systems. We present in this paper an innovative platform performing a real-time closed-loop between a cultured neural network and an artificial processing unit like a robotic interface. The system gathers bioware, hardware, and software components and ensures the closed-loop data processing in less than 50 mus. We detail here the system components and compare its performances to a recent commercial platform.

Automated parameter estimation of the hodgkin-huxley model using the differential evolution algorithm: Application to neuromimetic analog integrated circuits

We present a study on wavelet detection methods of neuronal action potentials (APs). Our final goal is to implement the selected algorithms on custom integrated electronics for on-line processing of neural signals; therefore we take real-time computing as a hard specification and silicon area as a price to pay. Using simulated neural signals including APs, we characterize an efficient wavelet method for AP extraction by evaluating its detection rate and its implementation cost. We compare software implementation for three methods: adaptive threshold, discrete wavelet transform (DWT), and stationary wavelet transform (SWT). We evaluate detection rate and implementation cost for detection functions dynamically comparing a signal with an adaptive threshold proportional to its SD, where the signal is the raw neural signal, respectively: (i) non-processed; (ii) processed by a DWT; (iii) processed by a SWT. We also use different mother wavelets and test different data formats to set an optimal compromise between accuracy and silicon cost. Detection accuracy is evaluated together with false negative and false positive detections. Simulation results show that for on-line AP detection implemented on a configurable digital integrated circuit, APs underneath the noise level can be detected using SWT with a well-selected mother wavelet, combined to an adaptive threshold.