Noëlle Lewis

Generation of Locomotor-Like Activity in the Isolated Rat Spinal Cord Using Intraspinal Electrical Microstimulation Driven by a Digital Neuromorphic CPG

Neural prostheses based on electrical microstimulation offer promising perspectives to restore functions following lesions of the central nervous system (CNS). They require the identification of appropriate stimulation sites and the coordination of their activation to achieve the restoration of functional activity. On the long term, a challenging perspective is to control microstimulation by artificial neural networks hybridized to the living tissue. Regarding the use of this strategy to restore locomotor activity in the spinal cord, to date, there has been no proof of principle of such hybrid approach driving intraspinal microstimulation (ISMS). Here, we address a first step toward this goal in the neonatal rat spinal cord isolated ex vivo, which can display locomotor-like activity while offering an easy access to intraspinal circuitry. Microelectrode arrays were inserted in the lumbar region to determine appropriate stimulation sites to elicit elementary bursting patterns on bilateral L2/L5 ventral roots. Two intraspinal sites were identified at L1 level, one on each side of the spinal cord laterally from the midline and approximately at a median position dorso-ventrally. An artificial CPG implemented on digital integrated circuit (FPGA) was built to generate alternating activity and was hybridized to the living spinal cord to drive electrical microstimulation on these two identified sites. Using this strategy, sustained left-right and flexor-extensor alternating activity on bilateral L2/L5 ventral roots could be generated in either whole or thoracically transected spinal cords. These results are a first step toward hybrid artificial/biological solutions based on electrical microstimulation for the restoration of lost function in the injured CNS.

In-vitro exposure of neuronal networks to the GSM-1800 signal.

The central nervous system is the most likely target of mobile telephony radiofrequency (RF) field exposure in terms of biological effects. Several electroencephalography (EEG) studies have reported variations in the alpha-band power spectrum during and/or after RF exposure, in resting EEG and during sleep. In this context, the observation of the spontaneous electrical activity of neuronal networks under RF exposure can be an efficient tool to detect the occurrence of low-level RF effects on the nervous system. Our research group has developed a dedicated experimental setup in the GHz range for the simultaneous exposure of neuronal networks and monitoring of electrical activity. A transverse electromagnetic (TEM) cell was used to expose the neuronal networks to GSM-1800 signals at a SAR level of 3.2 W/kg. Recording of the neuronal electrical activity and detection of the extracellular spikes and bursts under exposure were performed using microelectrode arrays (MEAs). This work provides the proof of feasibility and preliminary results of the integrated investigation regarding exposure setup, culture of the neuronal network, recording of the electrical activity, and analysis of the signals obtained under RF exposure. In this pilot study on 16 cultures, there was a 30% reversible decrease in firing rate (FR) and bursting rate (BR) during a 3 min exposure to RF. Additional experiments are needed to further characterize this effect.

An Embedded Deep Brain Stimulator for Biphasic Chronic Experiments in Freely Moving Rodents

This paper describes a Deep Brain Stimulation device, portable, for chronic experiments on rodents in the context of Parkinsons disease. Our goal is to equip the animal with a device that mimics the human therapeutic conditions. It implies to respect a set of properties such as bilateral current-mode and charge-balanced stimulation, as well as programmability, low power consumption and re-usability to finally reach a suitable weight for long-term experiments. After the analysis of the solutions found in the literature, the full design of the device is explained. First, the stimulation front-end circuit driven by a processor unit, then the choice of supply sources which is a critical point for the weight and life-time of our system. Our low cost system has been realized using commercial discrete components and the overall power consumption was minimized. We achieved 6 days of maximal current stimulation with the chosen battery for a weight of 13.8 g. Finally, the device was carried out in vivo on rats during a 3 weeks experiment as the used implantation technique allows battery changing. This experiment also permits to emphasize the mechanical aspects including the packaging and electrodes holding.

Scaling Rules For Mos Analog Design Reuse

In this paper we propose a methodology for analog design reuse during technology scaling. This method is based on resizing rules resulting in the application of a MOS transistor model. The aims of this scaling are the conservation of the performances of the original circuit and the reduction of power consumption and area. This resizing methodology has been applied on different analog circuits. The original circuit has been designed in 0.8 mum AMS technology with a supply voltage of 5 V and then scaled in 0.35 mum AMS technology with a 3.3 V supply voltage. Finally, the methodology is validated by simulation results

A CMOS Resizing Methodology for Analog Circuits

This article presents a CMOS resizing methodology for analog circuits during a technology migration, with easy-to-apply scaling rules based on a simple MOS transistor model. The goals are to transpose a circuit topology from one technology to another while preserving the main figures of merit and to quickly calculate the new transistor dimensions.

Application of IP-Based Analog Platforms in the Design of Neuromimetic Integrated Circuits

Reuse methodologies are now widely used to design digital circuits. They are based on the concept of intellectual property (IP), or virtual block of computing, characterized by a behavioral model, synthesizable or not. The design reuse for analog integrated systems is much less natural and less standardized. This paper addresses the issue of an analog design flow based on reuse, focusing on three key issues: the formal content of the IP block, the design of a reusable analog IP, and the organization of a design flow centered on an IP library. After a conceptual overview, this paper presents the methodological principles and details examples with a tutorial intention. The objective is to guide the designer involved in the process of developing analog IPs and corresponding design flow. This method is inspired by platform-based design and adapted here on an original case study: the design of full-custom neuromimetic integrated circuits, built from specific analog computational blocks. The development of reusable IPs represents an additional effort, mainly for behavioral modeling and characterization. Nevertheless, the steps illustrated in this case study show that the extra time provides a definite advantage to future design projects.

Behavioral modeling of noise in discrete time systems with VHDL-AMS application to a sigma-delta modulator

This paper presents the behavioral models of sigma-delta modulators and transient noise sources, using the standard language VHDL-AMS. The models are implemented in the time domain and their generic parameters are related to spectral characteristics. The objective of this work is to simulate noise effects in discrete time circuits and systems (like switched capacitors systems) at the behavioral level in order to minimize the simulation runtime required to evaluate and quantify the systems performance.

An IC-based controllable stimulator for respiratory muscle stimulation investigations

Functional Electrical Stimulation can be used to restore motor functions loss consecutive to spinal cord injury, such as respiratory deficiency due to paralysis of ventilatory muscles. This paper presents a fully configurable IC-centered stimulator designed to investigate muscle stimulation paradigms. It provides 8 current stimulation channels with high-voltage compliance and real-time operation capabilities, to enable a wide range of FES applications. The stimulator can be used in a standalone mode, or within a closed-loop setup. Primary in vivo results show successful drive of respiratory muscles stimulation using a computer-based dedicated controller.

Theoretical study and optimisation of a standard deviation estimator circuit for adaptive threshold spike detection

Summary This paper presents a theoretical study and the resulting architecture of an analogue-based standard deviation (SD) estimator, typically used in biomedical spike detectors to assess the noise level of bioelectrical recordings online. This well-known circuit generated a significant inaccuracy, so the aim was to increase the efficiency of spike detection through proper calculation of the noise SD, by developing a rigorous, original theoretical study. The approach consisted of establishing behavioural models for the SD estimation circuit to obtain a transfer function and compare different controllers. This modelling approach also highlighted the parameters available and the impact of their relationships on design optimisation. The behavioural models, inherently based on approximations, were then initially validated by comparing them with actual circuit behaviour, obtained using discrete components. These comparisons revealed that the models matched the actual circuit measurements. Finally, taking into account the conclusions of our theoretical study, an integrated version of this adaptive threshold spike detector was designed using 0.35-µm complementary metal–oxide–semiconductor technology. Simulations of this circuit revealed that the proposed controller eliminated the static error and ensured efficient spike detection. Copyright

CMOS differential neural amplifier with high input impedance

We present a CMOS differential neural amplifier with high input impedance, which topology is inspired by the instrumentation amplifier. The miniaturization of the MEAs goes with an increase of the electrodes impedance and necessitates high input impedance neural amplifiers; otherwise it results in a significant loss of signal and low SNR. The circuit presented here is designed on a 0.35 μm CMOS technology. Two versions are described which capacitive input impedance is 1 pF. One is robust to high input offset and consumes 13.5 μA; the other one is more sensitive to offset but consumes only 3.7 μA. Both generate less than 7 μVRMS input-referred noise and their NEF figures are respectively 8.4 and 3.66. These features are competitive in view of the literature on neural amplifiers, while the circuit was specifically designed to present a high input impedance.