Syunsuke Izumi

Structural analysis and reduction of in-grown stacking faults in 4H–SiC epilayers

We investigated the structure of in-grown stacking faults in the 4H–SiC(0001) epilayers. The in-grown stacking faults nucleate near the substrate/epilayer interface and expand the area with increasing epilayer thickness in a triangular shape. From transmission electron microscope observation, the formation of 1c of 8H polytype was confirmed in the in-grown stacking fault area. We also investigated the dependence of in-grown stacking fault density on the epitaxial growth rate, growth temperature, and substrate surface preparation.

Evaluation of Free Carrier Lifetime and Deep Levels of the Thick 4H-SiC Epilayers

Correlations between the free carrier lifetime of thick, lightly-doped n-type 4H-SiC epilayers and some deep levels (the Z1/2 center, the EH6/7 center and the D1 center) were investigated. Concentrations of the Z1/2 center and the EH6/7 center correlated with the measured carrier lifetime to some extent. We have also compared the free carrier lifetime measured by time-resolved photoluminescence (TRPL) measurement and microwave-detected photoconductive decay (μ-PCD) measurement. The carrier lifetime measured by both technique was in close agreement. The carrier lifetime measured by LTPL increased at an elevated temperature of 500 K.

Growth and Characterization of the 4H-SiC Epilayers on Substrates with Different Off-Cut Directions

Growth of thick 4H-SiC layers was performed on (0001) and (000-1) substrates off-cut towards <11-20> or <1-100>. The roughness of the epilayers grown on the four different substrates was almost the same level, at 0.20-0.23 nm, while the epilayers grown on (000-1) exhibited particular large epi-defects with densities 10-10 cm depending on the growth conditions. In both (0001) and (000-1), basal plane dislocations (BDs) inclined towards <1-100> with a tilt in the epilayer grown on substrates off-cut towards <1-100>, while the BDs lie along <11-20> for substrates off-cut towards <11-20>. No significant difference in densities of BDs and in-grown stacking faults for the different off-directions was revealed for (0001). For both (0001) and (000-1), the carrier lifetime of 4H-SiC epilayers was comparable for the different off-cut directions. Introduction High-voltage bipolar SiC devices withstanding more than 10 kV are attractive for power systems. Improvement or control of the minority carrier lifetime of SiC epilayers and the suppression of degradation of the forward characteristics are the current challenges for fabrication SiC bipolar devices [1]. Basal plane dislocations (BDs) in epilayers are reported as a source of forward degradation of the 4H-SiC pn diodes [2], while it is unclear why a number of basal plane dislocations propagate into the epilayer. To grow 4H-SiC epilayers, (0001) substrates off-angled towards <11-20> are commonly used. Growth of 4H-SiC epilayers with good morphology has been attained for 4H-SiC(0001) substrate off-cut towards <1-100> and (000-1) substrates off-cut towards <11-20> [3, 4], while the difference in propagation of dislocations, stacking faults or carrier lifetime between the epilayers grown on substrates off-cut towards <11-20> or <1-100> has not been reported in detail. In this paper, we compare the material quality of the 4H-SiC epilayers grown on (0001) and (000-1) substrates off-cut towards <11-20> or <1-100>. Experiment Growth of 4H-SiC epilayers was performed in a vertical hot-wall CVD reactor with a SiH4+C3H8+H2 system [5]. Typical growth temperature is ~1545oC at the susceptor top, and system pressure is controlled at 42 Torr. Prior to epitaxial growth, in-situ etching was performed using pure hydrogen at 1400oC under a system pressure of 30 Torr. Four different substrates, which were 4H-SiC(0001) and (000-1) off-cut 8o towards either <11-20> or <1-100>, were used. We varied C/Si ratio from 0.4 to 1.4 by changing only C3H8 flow rate, while SiH4 and H2 flow rates were fixed at 30 sccm and 10 slm, respectively. Morphology of the epilayers was evaluated by Nomarski optical microscope and atomic force microscope (AFM). Molten KOH etching at 480oC for 2 min was performed to investigate dislocations in the epilayers for (0001). X-ray topograph image for (11-28) reflection using a monochromator (λ=1.54Å) was taken for epilayers grown on (0001) and (000-1) substrates. The free carrier lifetime of the 4H-SiC epilayers was evaluated by time resolved photoluminescence (PL) using Materials Science Forum Online: 2004-06-15 ISSN: 1662-9752, Vols. 457-460, pp 229-232 doi:10.4028/www.scientific.net/MSF.457-460.229

Analysis of Structural Defects in the 4H-SiC Epilayers and their Influence on the Electrical Properties

We fabricated epi pn diodes and investigated the correlation between defects included in the 4H-SiC epilayers and the leakage current of the pn diodes. Threading edge dislocations, screw dislocations, basal plane dislocations and in-grown stacking faults existed in the epilayers. From EL images of the diodes under reverse bias voltage, it was found that a line of edge dislocations forming a grain boundary and some screw dislocations caused an increase in leakage current. We also mention the influence of dissociated micropipes.

Structure of In-Grown Stacking Faults in the 4H-SiC Epitaxial Layers

We investigated the structure of the in-grown stacking faults (SFs) in the 4H-SiC epilayers. The in-grown SFs exhibited the photoluminescence (PL) peaks representing phonon replicas with bandgap of 2.710 eV. The in-grown SFs were confirmed to be triangular-shaped by PL mapping and KOH etch pit observation. High-resolution TEM image showed that the in-grown SFs have an identical stacking sequence that differ from single or double Shockley SF. In addition, the density of the in-grown SF depended on growth conditions.

Dependence of Micropipe Dissociation on Surface Orientation

The influence of surface orientation and the off-cut direction of substrates on micropipe dissociation have been investigated. Micropipe dissociation was confirmed on epilayers grown on (0001) Siand (000-1) C-face substrates with the off-cut directions towards <11-20> and <1-100>. The line-shaped surface depressions on micropipes were visible and micropipe dissociation confirmed at a lower C/Si ratio (< C/Si = ~0.85) on the Si-face. On the other hand, the line-shaped depressions on micropipes were observed on epilayers grown at C/Si ratios of 0.4, 0.55, 0.7 and 0.85 on the C-face. Micropipe dissociation was also found on the C-face in a C/Si ratio range from 0.4 to at least 0.85.

Suppression of Leakage Current Increase of 4H-SiC Schottky Barrier Diodes during High-Temperature Annealing by "Face-to-Face" Arrangement

Ni/4H-SiC Schottky barrier diodes (SBDs) were fabricated by using “face-to-face” annealing technique. As a result, we can obtain the SBDs with low leakage current in the covered area of the bottom chip reproducibly. The leakage current of this are a is comparable to that of the samples without annealing. We found that the surface of this area wa s etched during annealing, and the increase in surface roughness was suppressed. Introduction SiC-SBDs have been expected to replace Si pin diodes by utilizing their properties with very low reverse recovery currents and high blocking voltages identical to Si pin diodes. However, there are several unsolved problems, one of which is unreproducibility of SBDs with low leakage c urrent. One of the difficulties to fabricate high voltage SiC devices is that an ion implantation and a high temperature annealing for the formation of guard ring structure c an cause a rough surface. We have reported that the leakage current of 4H-SiC-SBDs tend to increas e with annealing temperature and that the strain region were formed near the surface during anneal ing, which corresponded to the bright spot of OBIC (Optical Beam Induced Current) [1]. We considered that the origin of this increased leakage current w ith due to high temperature annealing is the degradation of the surface morphology, such as step bunc hing [2]. It was reported that the annealing in SiH 4 atmosphere [3] and the annealing with SiC cap upon the SiC wafer [4] are effective for suppression of surface roughness. To investigate the influence of the surface morphology, we fabricated Ni/4H-SiC-SBDs by “face-to-face” anne li g technique, because of its convenience, and evaluated the leakage current. Experiment The SBDs were fabricated on N-type 4H-SiC (0001) substrate with e p axial layer with the thickness of 10 μm and the doping concentration of 5.9x10 15 cm purchased from Cree, Inc. . The diameter of a Ni Schottky electrode was 200 μm. Although implantation to fabricate the guard ring was not done, the samples were annealed in a furnace assuming act ivation annealing. The Materials Science Forum Online: 2003-09-15 ISSN: 1662-9752, Vols. 433-436, pp 685-688 doi:10.4028/www.scientific.net/MSF.433-436.685