Kunikaza Izumi

Evaluation of Free Carrier Lifetime and Deep Levels of the Thick 4H-SiC Epilayers

Correlations between the free carrier lifetime of thick, lightly-doped n-type 4H-SiC epilayers and some deep levels (the Z1/2 center, the EH6/7 center and the D1 center) were investigated. Concentrations of the Z1/2 center and the EH6/7 center correlated with the measured carrier lifetime to some extent. We have also compared the free carrier lifetime measured by time-resolved photoluminescence (TRPL) measurement and microwave-detected photoconductive decay (μ-PCD) measurement. The carrier lifetime measured by both technique was in close agreement. The carrier lifetime measured by LTPL increased at an elevated temperature of 500 K.

Investigation of Basal Plane Dislocations in the 4H-SiC Epilayers Grown on {0001} Substrates

In this paper, we investigated the density of basal plane dislocations (BPDs) in 4H-SiC epilayers grown on (0001) and (000-1). Re-polishing of the substrate surface, in-situ H2 etching and off-cut angle were found to influence the propagation of BPDs into the epilayers. The epitaxial growth on (000-1) substrates yields a relatively low density of BPDs compared to growth on (0001). The electrical characteristics of pn diodes were also investigated, and the suppressed forward degradation and high-voltage blocking performance were obtained in the use of the (000-1) epilayers.

Growth and Characterization of the 4H-SiC Epilayers on Substrates with Different Off-Cut Directions

Growth of thick 4H-SiC layers was performed on (0001) and (000-1) substrates off-cut towards <11-20> or <1-100>. The roughness of the epilayers grown on the four different substrates was almost the same level, at 0.20-0.23 nm, while the epilayers grown on (000-1) exhibited particular large epi-defects with densities 10-10 cm depending on the growth conditions. In both (0001) and (000-1), basal plane dislocations (BDs) inclined towards <1-100> with a tilt in the epilayer grown on substrates off-cut towards <1-100>, while the BDs lie along <11-20> for substrates off-cut towards <11-20>. No significant difference in densities of BDs and in-grown stacking faults for the different off-directions was revealed for (0001). For both (0001) and (000-1), the carrier lifetime of 4H-SiC epilayers was comparable for the different off-cut directions. Introduction High-voltage bipolar SiC devices withstanding more than 10 kV are attractive for power systems. Improvement or control of the minority carrier lifetime of SiC epilayers and the suppression of degradation of the forward characteristics are the current challenges for fabrication SiC bipolar devices [1]. Basal plane dislocations (BDs) in epilayers are reported as a source of forward degradation of the 4H-SiC pn diodes [2], while it is unclear why a number of basal plane dislocations propagate into the epilayer. To grow 4H-SiC epilayers, (0001) substrates off-angled towards <11-20> are commonly used. Growth of 4H-SiC epilayers with good morphology has been attained for 4H-SiC(0001) substrate off-cut towards <1-100> and (000-1) substrates off-cut towards <11-20> [3, 4], while the difference in propagation of dislocations, stacking faults or carrier lifetime between the epilayers grown on substrates off-cut towards <11-20> or <1-100> has not been reported in detail. In this paper, we compare the material quality of the 4H-SiC epilayers grown on (0001) and (000-1) substrates off-cut towards <11-20> or <1-100>. Experiment Growth of 4H-SiC epilayers was performed in a vertical hot-wall CVD reactor with a SiH4+C3H8+H2 system [5]. Typical growth temperature is ~1545oC at the susceptor top, and system pressure is controlled at 42 Torr. Prior to epitaxial growth, in-situ etching was performed using pure hydrogen at 1400oC under a system pressure of 30 Torr. Four different substrates, which were 4H-SiC(0001) and (000-1) off-cut 8o towards either <11-20> or <1-100>, were used. We varied C/Si ratio from 0.4 to 1.4 by changing only C3H8 flow rate, while SiH4 and H2 flow rates were fixed at 30 sccm and 10 slm, respectively. Morphology of the epilayers was evaluated by Nomarski optical microscope and atomic force microscope (AFM). Molten KOH etching at 480oC for 2 min was performed to investigate dislocations in the epilayers for (0001). X-ray topograph image for (11-28) reflection using a monochromator (λ=1.54Å) was taken for epilayers grown on (0001) and (000-1) substrates. The free carrier lifetime of the 4H-SiC epilayers was evaluated by time resolved photoluminescence (PL) using Materials Science Forum Online: 2004-06-15 ISSN: 1662-9752, Vols. 457-460, pp 229-232 doi:10.4028/www.scientific.net/MSF.457-460.229

Structure of In-Grown Stacking Faults in the 4H-SiC Epitaxial Layers

We investigated the structure of the in-grown stacking faults (SFs) in the 4H-SiC epilayers. The in-grown SFs exhibited the photoluminescence (PL) peaks representing phonon replicas with bandgap of 2.710 eV. The in-grown SFs were confirmed to be triangular-shaped by PL mapping and KOH etch pit observation. High-resolution TEM image showed that the in-grown SFs have an identical stacking sequence that differ from single or double Shockley SF. In addition, the density of the in-grown SF depended on growth conditions.

4H-SiC Epitaxial Growth for High-Power Devices

4H-SiC epilayers are grown in a vertical hot-wall reactor with an inner susceptor configuration. Reduction of micropipe density can be achieved by chemic al vapor deposition (CVD) growth using SiH4 and C3H8 as source gases. This technique involves dissociation of micropipes into elementary screw dislocations by growth of a micr opipe stop (MS) layer. The most important parameter to control micropipe dissociation was found to be C/Si ratios of the source gases. A high probability of micropipe dissociation is obtai ned at a relatively low C/Si ratio. Meanwhile we have succeeded in closing more than 99.6% of m icropipes in a commercial 4H-SiC substrate by a single growth run. Low-doped active layers ar grown at a relatively high C/Si ratio onto MS layers without coalescing of elementary sc rew dislocations. A large Schottky barrier diode (SBD) with a diameter of 11.2 mm φ was fabricated using this technique. We also discuss growth of very thick 4H-SiC epilayers at a high growth rate and other i ssu s.

Improvement in Electrical Performance of Schottky Contacts for High-Voltage Diode

We investigated the effect of high temperature annealing on the Schottky barrier height (Fb) and the ideality factor (n-factor) of a Mo contact. In a Mo contact, the Fb increased and the leakage current decreased by annealing at 600oC, while no increase in n-factor and forward excess current owing to the high temperature annealing was observed. The Schottky barrier diode with Mo contact annealed at 600oC showed a blocking-voltage (Vb) of 4.15 kV and a specific on resistance (Ron) of 9.07 mWcm2, achieving a high Vb 2/Ron value of 1898 MW/cm2.

Conditions for Micropipe Dissociation by 4H-SiC CVD Growth

4H-SiC epilayers are grown by chemical vapor deposition (CVD) unde r a various C/Si ratio of source gases. At a relatively low C/Si ratio, micropipes are dissociated into several closed-core screw dislocations in a high probability. Correspondingly, line-shaped surface depressions are generated at a relatively low C/Si ratio. Thus, based on the morphological observation on the epilayers grown under a various C/Si ratio, conditions and mechanisms for micropipe dissociation have been discussed. Introduction SiC has excellent properties and it is suitable for high power and low-loss applications. In these days, some prototype SiC devices with a very high reverse blocking vol ta e have been reported [1]. Moreover commercial SiC diodes have recently been produced [2]. However, it is still difficult to fabricate large SiC devices with a high yield. It is understood that a high defect density in SiC substrates and epilayers is the main cause of thi s problem. Thus a reduction of the defects in substrates and epilayers is required. The micropipe is a major defect in SiC substrates, and it was known that micropipes in substrates propagate t o th epilayer by conventional chemical vapor deposition (CVD). Thus, liquid phase epitaxy ( LPE) was expected to be a micropipe reduction method [3]. Recently we found tha t some micropipes were dissociated into several closed-core screw dislocations during CVD growth [4]. On this occasion, we succeeded in finding a controlling method of micropipe disso ciation by adjusting the C/Si ratio in reactant gases during growth [5, 6]. In this paper, we conside r the r lationship between micropipe dissociation and growth conditions based on the surface morphology.

Dependence of Micropipe Dissociation on Surface Orientation

The influence of surface orientation and the off-cut direction of substrates on micropipe dissociation have been investigated. Micropipe dissociation was confirmed on epilayers grown on (0001) Siand (000-1) C-face substrates with the off-cut directions towards <11-20> and <1-100>. The line-shaped surface depressions on micropipes were visible and micropipe dissociation confirmed at a lower C/Si ratio (< C/Si = ~0.85) on the Si-face. On the other hand, the line-shaped depressions on micropipes were observed on epilayers grown at C/Si ratios of 0.4, 0.55, 0.7 and 0.85 on the C-face. Micropipe dissociation was also found on the C-face in a C/Si ratio range from 0.4 to at least 0.85.