T. H. Yang

Overlay target design and evaluation for SADP process

Overlay performance has been a critical factor for advanced semiconductor manufacturing for years. Over time these requirements become more stringent as design rules shrink. Overlay mark design and selection are the first two steps of overlay control, and it is known that different overlay mark designs will have different responses to process conditions. An overlay mark optimized for traditional process might not be suitable for SADP (self-aligned double patterning) technology due to changes in lithography and etching process conditions. For instance, the traditional BIB (box-in-box) target defined by the core mask becomes a template structure in SADP flow, the pitch and cycle of the overlay mark is further changed after spacer formation and core film removal hence the mark recognition and robustness have been challenging for the subsequent process layers. The comprehensive study on the methodology of overlay mark design and selection is still not available for SADP process. In this paper, various types of overlay marks were designed to comply with the SADP process to get rid of the weaknesses of traditional targets. TMU (total measurement uncertainty) performance was adopted to determine the optimal overlay marks for meeting production overlay control requirements in SADP process flow. The results have suggested the segmented marks outperform to non-segmented marks on image contrast as well as TMU.

A comprehensive comparison between double patterning and double patterning with spacer on sub-50nm product implementation

In this study, DP (Double Patterning) and DPS (Double Patterning with Spacer) were comprehensively compared through word line layout of 50nm node product, and special focus was put on the assessments of layout discontinuity zones through experimental validation. In conventional flash manufacturing, the lithographic proximity effect and etch loading effect around the array-gap zones have been inherent characteristics to be addressed. For DP process, apart from the overlay error induced pattern displacement and CD non-uniformity, the cross-coupling effects between adjacent features around the array-gap zones by two photo and two etch steps have further complicated the process optimization, therefore careful exploration was carried out to indicate the challenges on process optimization. The DPS can maintain good resultant CD uniformity of dense array through precisely programmed exposure CD and spacer thickness, it may also keep away from the proximity around array-gap zones. But, the second exposure is necessary for trimming the unwanted patterns and delineating the peripheral patterns. In purpose of trimming the unwanted patterns at array-gap zone in the 2nd exposure, the overlay registration will account for the CD control of boundary lines as well as the defectivity around this area.

Novel ATHENA mark design to enhance alignment quality in double patterning with spacer process

DPS (Double Patterning with Spacer) has been one of the most promising solutions in flash memory device manufacturing. Apart from the process complexity inherent with the DPS process, the DPS process also requires more engineering efforts on alignment technique compared to the single patterning. Since the traditional alignment marks defined by the core mask has been altered hence the alignment mark recognition could be challenging for the subsequent process layers. This study characterizes the process influence on the traditional ASML VSPM (Versatile Scribelane Primary Marks) alignment mark, and various types of sub-segmentations within VSPM marks were carried out to enable the alignment and find out the best performing alignment marks. The design of the transverse and vertical sub-segmentations within the VSPM marks is aimed to enhance the alignment signal strength and mark detectability. Alignment indicators of WQ (Wafer Quality), MCC (Multiple Correlation Coefficient) and ROPI (Residual Overlay Performance Indicator) were used to judge the alignment performance and stability. A good correlation was established between sub-segmentations and wafer alignment signal strength.

Multiple-step process window aware OPC for hyper-NA lithography

To avoid the dramatically diminishing of lithography process window as the shrink of design rule, the implementation of process-aware optical proximity correction (PWOPC) has been indispensable. The conventional PWOPC is capable of reducing CD variation at off-focus-off-dose conditions for the worst hotspot but some new weak points might be generated due to over compensation from compromising with the worst hotspot. In this paper, a so-called “multiple-step process aware OPC”, was demonstrated for maintaining better process window for all hotspots via damascene metal layer in 43nm half-pitch design. Through isolating the hotspots from the chip layout, different CD tolerances can be applied for the various types of hotspots to avoid the conflicts between different requirements. Increased levels of CD-tolerance could be applied in the multiple-step PWOPC flow for the layout with a great number of weak points. The ultimate aim of the multiple-step PWOPC operation is maintaining sufficient process window for entire layout. The performance comparison was carried out among nominal OPC, conventional PWOPC and multiple-step PWOPC flows for contour CD within appropriate process window, turn around time of layout correction and CD distribution of hotspots.

SMO and NTD for robust single exposure solution on contact patterning for 40nm node flash memory devices

Contact-hole patterning is even more challenging than line/space patterning because of the lower image contrast and smaller process window. To enable single exposure solution of 40-45nm half pitch contact-hole at this nearly resolvable limit of current 1.35NA ArF immersion lithography, negative tone development (NTD) process, source mask co-optimization (SMO) methodology and free-form source were explored in this study. The optimization of free form source and mask for NTD process was firstly carried out via Brion Tachyon SMOTM software. The wafer-level performance was then compared for different mask layout solutions and different mask types. A manufacture worthy process window was achieved for 40nm technology node Flash memory product through the combination of free-from source, SMO and NTD technologies. In the performance comparison for mask types, 6% HTPSM performed wider DoF and exposure latitude for all three pitch designs. But OMOG mask is superior to 6% HTPSM on mask and wafer CD uniformity. To further improve the overlapping process window, preserving the SMO layout solution as possible for the sparse environments and minimizing the SRAF writing errors were proposed as the two most critical tuning knobs.

Process solutions for reducing PR residue over non-planar wafer

SAS (Self-Aligned Source) process has been widely adopted on manufacturing NOR Flash devices. To form the SAS structure, the compromise between small space patterning and sufficiently removing photo resist residue in topographical substrate has been a critical challenge as the device scaling down. In this study, photo simulation, layout optimization, resist processing and tri-layer materials were evaluated to form defect-free and highly extendible SAS structure for NOR Flash devices. Photo simulation suggested more coherent light source allowed the incident light to reach the trench bottom that facilitates the removal of photo resist. Mask bias also benefited the process latitude extension for residue-free SAS printing. In the photo resist processing, both lowering the SB (Soft Bake) and raising PEB (Post-Exposure Bake) temperature of photo resist were helpful to broaden the process window but the final pattern profile was not good enough. Thermal flow for pos-exposure pattern shrinkage achieved small CD (Critical Dimension) patterning with residue-free, however the materials loading effect is another issue to be addressed at memory array boundary. Tri-layer scheme demonstrated good results in terms of free from residue, better substrate reflectivity control, enabling smaller space printing to loosen overlay specification and minimizing the poly gate clipping defect. It was finally proposed to combine with etch effort to from the SAS structure. Besides it is also promising to extend to even smaller technology nodes.

Image-assistant OPC model calibration on 65nm node contact layer

This work compared the CD-based and image-assistant approaches for calibrating the OPC models. OPC models were first developed for 65nm-node memory contact layer and calibrated by contact test patterns with various ellipticities. The image-assistant model is a hybrid one calibrated by SEM contours and 1D measurement results, while the CD-based model calibration uses 1D measurement results as the sole data source. The fitting errors, model prediction ability and OPCed results were compared between these two models. Besides, the challenges on calibrating the edge-detection algorithm of the CD SEM images to the extracted contours of OPC tool were also discussed. Finally, the layouts corrected by CD-based and image-assistant models were written on a test mask for wafer-level comparison. The results displayed that the CD-based model showed smaller error on fitting and interpolation, but image-assistant model got improvement on extrapolation prediction of array-edge contact, unknown contact pattern and long contacts. The wafer-level comparison also revealed the image-assistant model outperformed to the CD-based model by smaller correction error on unexpected patterns.

Contact formation with extremely low proximity effect by double patterning technology

Contact hole within a NOR FLASH memory array is one of the most challenging features to print in the semiconductor manufacturing. It has been the key limiter of NOR FLASH memory scaling due to the difficulties involved in patterning the one-dimensional contact arrays and extremely stringent contact to gate overlay constraints. In this study, DPT (Double Patterning Technology) by ArF dry process was introduced for patterning NOR FLASH memory contact arrays. This approach has demonstrated a contact patterning with extremely low optical proximity effect for 50nm half-pitch with satisfied lithography process latitude and especially the circular contact shape can be maintained without compromise of NOR FLASH cell area. The novel hard mask scheme was the key enabler for this contact double patterning and this approach can be easily extended to ArF immersion lithography as a promising option for contact formation in leading-edge memory products.

Analysis of pattern density on process proximity compensation

The challenges of ever-smaller CD (Critical Dimension) budget for advanced memory product requires tight ACLV (Across-Chip Line-width Variation) control. In addition to the lithographic MOPC (Model-based Optical Proximity Correction) for DCD (photo CD) control, the process correction for etch proximity effect can no longer be ignored. To meet on our requirement on final CD accuracy for critical layer, a set of test pattern, that represents memory array in one of our critical layers, has been generated for both photo and etch process characterizations. Through the combination of different pattern-coverage areas in the test mask and wafer map design, various local (chip-level) pattern densities of 40%~70% and global (wafer-level) pattern densities of 35%~65% were achieved for optical and etch proximity study. The key contributors to the process proximity effect were identified and voluminous data has been extracted from the memory block like patterns for statistical analysis. The photo and etch proximity effects were hence modeled as function of memory block separation, local pattern density as well as global pattern density. Finally, the respective photo and etch proximity effects through model-based proximity correction and rule-based proximity correction were applied in a multi-step flow to products.

Overlay degradation induced by film stress

The semiconductor industry has continually sought the approaches to produce memory devices with increased memory cells per memory die. One way to meet the increasing storage capacity demand and reduce bit cost of NAND flash memories is 3D stacked flash cell array. In constructing 3D NAND flash memories, increasing the number of stacked layers to build more memory cell number per unit area necessitates many high-aspect-ratio etching processes accordingly the incorporation of thick and unique etching hard-mask scheme has been indispensable. However, the ever increasingly thick requirement on etching hard-mask has made the hard-mask film stress control extremely important for maintaining good process qualities. The residual film stress alters the wafer shape consequently several process impacts have been readily observed across wafer, such as wafer chucking error on scanner, film peeling, materials coating and baking defects, critical dimension (CD) non-uniformity and overlay degradation. This work investigates the overlay and residual order performance indicator (ROPI) degradation coupling with increasingly thick advanced patterning film (APF) etching hard-mask. Various APF films deposited by plasma enhanced chemical vapor deposition (PECVD) method under different deposition temperatures, chemicals combinations, radio frequency powers and chamber pressures were carried out. And -342MPa to +80MPa film stress with different film thicknesses were generated for the overlay performance study. The results revealed the overlay degradation doesn’t directly correlate with convex or concave wafer shapes but the magnitude of residual APF film stress, while increasing the APF thickness will worsen the overlay performance and ROPI strongly. High-stress APF film was also observed to enhance the scanner chucking difference and lead to more serious wafer to wafer overlay variation. To reduce the overlay degradation from ever increasingly thick APF etching hard-mask, optimizing the film stress of APF is the most effective way and high order overlay compensation is also helpful.