T. Melde

Analysis of TANOS Memory Cells With Sealing Oxide Containing Blocking Dielectric

In this paper, we investigate the specific impact of an additional silicon oxide layer (sealing oxide) on top of the charge-trap nitride on the electrical performance of small-dimension and large TANOS charge-trapping (CT) memory cells. We observe a significant improvement in charge retention on both our target 48-nm NAND TANOS cells and on large 5 μm long and wide memory cells. However, erase performance is partially degraded by this additional silicon dioxide top-dielectric layer. The presented intrinsic CT stack retention for 3.5-nm sealing oxide, which is visible on large cell structures, clearly shows the potential for multilevel cell operation.We further identified trapping in the Al2O3 states of the blocking dielectric to improve the program and erase performance of conventional TANOS memory cells. However, detrapping from these trap states was found to be the root cause of insufficient retention.

Nitride Thickness Scaling Limitations in TANOS Charge Trapping Devices

This article demonstrates that the scaling of the charge trap layer leads to an increasing charge loss in retention mode. This result is assigned to the fact that the blocking aluminum oxide is the main leakage path. It is further presented that the charge distribution moves towards the top oxide during programming and therefore shortens the distance to the leakage path. For thinner charge trap layers, the traps close to the aluminum oxide interface are already filled at lower DeltaVt resulting in higher retention loss for the same Vt shift.

Anomalous Erase Behavior in Charge Trapping Memory Cells

This article details an anomalous erase behavior in charge trapping memory devices which is visible in a characteristic erase hump in transient erase curves. For an initial period of time a Vt increase is seen when erase condition are applied to virgin cells before the expected erasing takes place for longer erase pulse duration. This is attributed to charges injected from the gate corners to the areas above source and drain. This effect significantly deteriorates the erase performance of charge trapping devices compared to the intrinsic erase behavior which can be measured at large area capacitor structures.

Select Device Disturb Phenomenon in TANOS NAND Flash Memories

This letter investigates a new select device disturb phenomenon in TANOS NAND flash memories. Since NAND string select devices contain the same charge trap (CT) stack as the memory cells, they are, in principle, programmable. We observe a select threshold voltage increase during cycling of the cell array. This disturb is caused by electron injection from the outermost wordline into the CT layer of the select devices under the erase condition. The increasing select threshold voltage leads to a reduced string current and, finally, to read fails of the NAND string. The mechanism is evaluated by means of electrical measurements and field simulations. Several options to overcome this issue are proposed.

TaN and

The sidewall gate-etch damage influence on the electrical behavior of 48-nm TaN/AI2O3/SiN/SiO2/Si (TANOS) NAND charge-trapping memory cells is investigated in detail. This etch damage occurs at the sidewall of the high work-function TaN metal gate and high-k AI2O3 blocking-oxide layers and adversely affects the electrical performance and the mechanical stability of small-ground-rule TANOS cells. Both issues could be solved for 48-nm TANOS cells by the introduction of a new integration scheme, which includes a removable encapsulation liner. This SiN liner protects the TaN sidewall from the etch damage during the aggressive AI2O3 high-k etch process. The optimum of the 48-nm electrical cell performance was found for a 4-nm encapsulation liner thickness. In contrast to 48-nm TANOS cells, the encapsulation liner thickness does not affect the electrical performance of large 5-μm-long-and-wide memory cells. The memory cell performance dependence on the TANOS liner thickness and memory cell size is explained by a damaged AI2O3 region approximately 3-4 nm thick at the block oxide side wall. As a result, the reported etch damage exhibits a new scaling issue for TANOS memory cells around the 20-nm technology node when the total encapsulation liner thickness approaches half of the memory cell length.

\hbox{Al}_{2}\hbox{O}_{3}

In this work we present a systematic investigation concerning the correlation of Random Telegraph Noise (RTN) with erratic bits in sub-50 nm floating gate NAND memory cells. Both effects are compared with respect to their implication in reliability and cell operation parameters of sub-50 nm flash devices. Related measurements were performed on a test chip with large floating gate cell arrays in NAND architecture. The analysis methods for both effects are presented comparing the magnitude and cycling stress dependency in detail. Additionally, two integration concepts with different memory cell sidewall oxidation approaches are discussed effecting differently the RTN and erratic programming behavior. Based on the characterization results we conclude that both effects are originating from different trap mechanisms. Possible explanations for the different trap mechanisms and locations are discussed.

Sidewall Gate-Etch Damage Influence on Program, Erase, and Retention of Sub-50-nm TANOS nand Flash Memory Cells

This publication investigates the program simulation of charge trapping memory devices in detail. Three different aspects of the simulation are highlighted which have a major impact on the program characteristics in trap based memories. The analysis is done by a comparison between measurement and simulation. It is shown that the trap capture cross section, the bottom oxide to storage nitride energy band offset and the tunneling injection point, under modified Fowler-Nordheim tunneling conditions, are of major importance for highly accurate simulations. The results provide deeper insight into the mechanisms dominating the program behavior in charge trapping memory devices.

Analysis of trap mechanisms responsible for Random Telegraph Noise and erratic programming on sub-50nm floating gate flash memories

This paper presents charge trapping (CT) cells integrated with a sacrificial liner at the word line (WL) side wall which improves significantly the erase and retention characteristics, currently the main issues in CT memory devices.

Accurate program simulation of TANOS charge trapping devices

This paper investigates the use of a metal control gate for sub 30 nm NAND flash memory. It is shown that polysilicon control gates are not effective at reduced feature sizes due to poor electrical conductivity. As the physical dimensions scale and the doping level of the polysilicon decreases, especially at the beginning of polysilicon deposition, the control gate plugs become electrically non-functional. This isThis paper investigates the use of a metal control gate for sub 30 nm NAND Flash memory. It is shown that polysilicon control gates are not effective at reduced feature sizes due to poor electrical conductivity. As the physical dimensions scale and the doping level of the polysilicon decreases, especially at the beginning of polysilicon deposition, the control gate plugs become electrically non-functional. This is very critical in the narrow control gate plug where the polysilicon can become depleted. A TiN control gate is proposed and implemented in a 48 nm technology. It is shown to eliminate the depletion effect and to have comparable electrical results to a polysilicon control cell. very critical in the narrow control gate plug where the polysilicon can become depleted. A TiN control gate is proposed and implemented in a 48 nm technology. It is shown to eliminate the depletion effect and to have comparable electrical results to a polysilicon control cell.

Improvement of 48 nm TANOS NAND Cell Performance by Introduction of a Removable Encapsulation Liner

In our work we present statistical methods and new memory array analysis approaches for decomposition and assessment of contributors to the Vth distribution widening. There, cell threshold voltage characteristics along bitlines and wordlines are considered as well as hidden systematic effects by convolutional analysis. Based on investigations on sub-50 nm floating gate NAND memory arrays we demonstrate an analysis method to distinguish between different reasons for broadened distributions by means of memory map analysis algorithms and filters. The impact of systematic threshold voltage and cell current variation in memory arrays caused by intrinsic circuit properties will be discussed.