T. Schulz

Multi-gate devices for the 32nm technology node and beyond

Due to the limited control of the short channel effects, the high junction leakage caused by band-to-band tunneling and the dramatically increased VT statistical fluctuations, the scaling of planar bulk MOSFETs becomes more and more problematic with every technology node. The ITRS roadmap predicts that from the 32 nm technology node on planar bulk devices will not be able to meet the stringent leakage requirements anymore and that multi-gate devices will be required. In this paper, the suitability of FinFET based multi-gate devices for the 32 nm technology and beyond will be discussed. Apart from the benefits, some technological challenges will be addressed.

Low-temperature electron mobility in Trigate SOI MOSFETs

Evidence of one-dimensional subband formation is found at low temperature in trigate silicon-on-insulator MOSFETs, resulting in oscillations of the I/sub D/(V/sub G/) characteristics. These oscillations correspond to the filling of energy subbands by electrons as the gate voltage is increased. High mobility, reaching 1200 cm/sup 2//Vs, is measured in the subbands at T=4.4 K. Subband mobility decreases as temperature is increased. Conduction in subbands disappears for temperatures higher than 100 K or for drain voltage values that are significantly larger than kT/q.

Novel dual bit tri-gate charge trapping memory devices

Dual bit operation of fabricated tri-gate nonvolatile memory devices with aggressively scaled oxide-nitride-oxide (ONO) dielectrics is presented for the first time. Compared to a planar cell, the proposed tri-gate device architecture offers higher readout currents and improved electrostatic gate control of the channel region yielding very good scalability of the devices. We have investigated devices with gate lengths in the range L/sub G/=100-220 nm and we focus on their write-erase, retention, and cycling characteristics.

Body effect in tri- and pi-gate SOI MOSFETs

A simple model based on the representation of capacitive coupling effects between the front- and back-gate and the channels, has been developed for tri-gate and pi-gate SOI MOSFETs. The model has been validated using numerical simulation of the body factor in such devices, as well as by experimental results. The body factor is much smaller than in regular, single-gate silicon-on-insulator devices because of the enhanced coupling between gate and channel and because the lateral gates shield the device from the electrostatic field from the back gate.

Temperature effects on trigate SOI MOSFETs

Trigate silicon-on-insulator (SOI) MOSFETs have been measured in the 5-400 K temperature range. The device fin width and height is 45 and 82 nm, respectively, and the p-type doping concentration in the channel is 6/spl times/10/sup 17/ cm/sup -3/. The subthreshold slope varies linearly with temperature as predicted by fully depleted SOI MOS theory. The mobility is phonon limited for temperatures larger than 100 K, while it is limited by surface roughness below that temperature. The corner effect, in which the device corners have a lower threshold voltage than the top and sidewall Si/SiO/sub 2/ interfaces, shows up at temperatures lower than 150 K.

Planar and vertical double gate concepts

Abstract In this paper, we report a comparative study of different double gate architectures. The main focus is on the fabrication method of two different device concepts developed in our group. The first is a planar version with special SOI wafers or deposited films and the second is a vertical transistor with lithography independent channel length. In addition to a thorough structural analysis we present electrical characteristics of the fabricated devices.

Radiation Dose Effects in Trigate SOI MOS Transistors

N-channel trigate SOI MOSFETs have been irradiated with 60 Co gamma rays at doses up to 6 Mrad(SiO2). The threshold voltage shift at 6 Mrad is less than 10 mV in transistors with a gate length of 0.3 mum. At 6 Mrad(SiO2), the current drive reduction in the same devices is 10% if VG=0 V during irradiation and 20% if VG=1 V during the irradiation. The generation of positive charges in the BOX increases the electron concentration at the bottom interface of the silicon fins. Inversion electrons at the bottom interface have a higher mobility than the electrons at the (110)-oriented fin sidewalls. As a result, an increase of transconductance with dose is observed at moderate doses [<1 Mrad(SiO2)]. At higher doses, the usual mobility degradation caused by interface trap generation is observed

Circuit design issues in multi-gate FET CMOS technologies

Multi-gate FETs are promising for sub-45nm CMOS technologies. To address the link between design and technology, basic digital and analog circuits are fabricated using FinFET and triple-gate FETs. Digital circuit performance, leakage currents, and power dissipation are characterized. The triple-gate FET achieves the lowest gate delay (27ps at 1.2V) and is >30% faster than FinFET with same oxide thickness of 2nm and gate lengths of 80nm. A FinFET-based Miller OpAmp achieves 45dB dc gain at 1.5V

An Effective Switching Current Methodology to Predict the Performance of Complex Digital Circuits

A new methodology to assess dynamic circuit performance using basic device currents is presented. In contrast to existing effective drive current calculation considering inverters only, our approach provides precise circuit delays of product-relevant NAND and NOR logic gates over a wide range of supply voltages. The relevance of currents in the linear regime for circuit performance in sub-65 nm CMOS technologies is demonstrated also experimentally by a 65% performance boost in complex multi-gate FET circuits.

Room-Temperature Low-Dimensional Effects in Pi-Gate SOI MOSFETs

Evidence of a one-dimensional subband formation is found in Pi-gate SOI MOSFETs at room temperature as oscillations are found in the ID(VG) characteristics. These oscillations correspond to an intersubband scattering. Even though the height-to-width ratio of the silicon fins is equal to five, the device behavior is better described by a one-dimensional semiconductor theory than by a two-dimensional gas model