T. Sugano

Single Electron Device with Asymmetric Tunnel Barriers

A single electron device with asymmetric tunnel barriers (ATBs) is proposed, and its operation simulated by computer. Current in the ATB structure is dominated by Fowler-Nordheim tunneling while that in a conventional symmetric tunnel barrier (STB) structure is determined by direct tunneling. Consequently, the ATB has two remarkable advantages over STB. First, the tunnel resistance of ATB depends on the energy of tunneling electron and is determined independently of the barrier capacitance. Second, the tunneling of electrons becomes almost unilateral in ATB and bilateral in STB. These advantages of ATB make it easier to fabricate single electron circuits with high speed, high temperature and low power consumption.

Geometry-induced fractal behaviour in a semiconductor billiard

We report geometry-induced fractal behaviour in the low-field magneto-conductance fluctuations of a mesoscopic semiconductor billiard. Such fractal behaviour was recently predicted to be induced by the mixed (chaotic/regular) phase space generated by the soft-walled billiard potential, and our results constitute a possible experimental observation of the infinite hierarchical nature of this mixed phase space. Preliminary investigations of the effects of temperature and gate bias, which directly control the electron coherence and billiard potential profile, are presented.

Suppression of short channel effects by full inversion in deep sub-micron gate SOI MOSFETs

Abstract Classical modeling of fully inverted SOI MOSFET (FI MOSFET) has been performed. In FI MOSFETs, the top Si layer is thinner than the thickness of the inversion layer at the conducting state and so the depleted region in the top Si layer is completely eliminated. It was found that the gate electric field induces carriers in the channel more effectively in FI MOSFET than in the fully depleted SOI MOSFETs (FD MOSFET), so that the short channel effects can be suppressed significantly.

Suppression of Drain-Induced Barrier Lowering in Silicon-on-Insulator MOSFETs Through Source/Drain Engineering for Low-Operating-Power System-on-Chip Applications

In this paper, the authors propose novel metal-oxide-semiconductor field-effect transistor (MOSFET) types featuring additional L-shaped counterdoped areas in the source and/or drain regions of silicon-on-insulator (SOI) MOSFETs to reduce drain-induced barrier lowering (DIBL) through the buried oxide (BOX) layer. The L-shaped region in the drain area shields the BOX layer from penetration by the drain electric field, thereby reducing DIBL in the body region. Simulation of the electrical characteristics of these novel MOSFETs demonstrated more remarkable DIBL suppression and subthreshold slope performance in short-channel regions than in conventional SOI MOSFETs. In addition to this suppression, these novel MOSFETs suppress breakdown voltage more effectively than conventional SOI MOSFETs. The authors concluded that the proposed devices are capable of contributing to the scaling of SOI MOSFETs in ultralarge-scale integration circuits.

Suppression of DIBL in deca-nano SOI MOSFETs by controlling permittivity and thickness of BOX layers

The Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) fabricated on a Silicon-On-Insulator (SOI) substrate is effective to suppress Short Channel Effect (SCE), and is one of the most promising electron devices for Very Large Scale Integration (VLSI) circuits for higher speed, higher integration density, and lower power consumption, and it has been already demonstrated that SCE in deep submicron SOI MOSFETs comes from Drain-Induced Barrier Lowering (DIBL) at SOI/Buried OXide (BOX) interface by the authors group. This paper elucidates the roles of permittivity and thickness of BOX layers in suppressing the DIBL in SOI MOSFETs by performing numerical device simulations of SOI MOSFETs with various permittivity and thickness of BOX systematically and by visualizing distribution of dielectric flux lines and current flow lines as well as contour potential lines in MOSFETs.

Periodic conductance fluctuations and lead-induced scarring in open quantum dots

We consider the nature of ballistic electron transport in open mesoscopic cavities, coupled to external reservoirs by means of few-mode quantum point contacts. The devices vary in size over a wide range and the discrete nature of their electronic energy spectrum is expected to strongly influence the resulting electrical behaviour. Electron interference is also an important process in these devices and is investigated through studies of their low-temperature magneto-resistance. This is found to be characterized by regular fluctuations, which numerical simulations reveal to be associated with periodically recurring wavefunction scarring. Further analysis shows that the scarring is established by the collimating action of the injecting point contact, the quantum mechanical nature of which ensures that just a few cavity modes are excited to participate in transport. We therefore conclude that chaotic scattering is suppressed in mesoscopic cavities once their discrete quantum mechanical nature becomes resolved. Transport then instead occurs via a small number of regular orbits, which are stabilized by the role of the quantum point contact leads and the discrete quantization within the cavity itself. These long orbits give rise to well defined wavefunction scarring with measurable magneto-transport results.

Preparation of starting materials of β-BaB2O4 by zone melting

Abstract Starting materials for the low temperature phase BaB2O4 (β-BBO) have been successfully synthesized by a zone melting technique using a non-wetting graphite boat under Ar atmosphere. Melt composition and zone refining of raw material are found to influence strongly the formation of β-phase. α- and β-phases tend to be formed from non-stoichiometric and stoichiometric melts, respectively. Zone melting using a zone refined raw material favors the formation of β-phase over the whole lenght of the ingot, independent of the composition of the starting mixture.

Quantitative Extraction of Electric Flux in the Buried-Oxide Layer and Investigation of Its Effects on MOSFET Characteristics

Silicon-on-insulator (SOI) MOSFETs have advantages over conventional bulk MOSFETs in terms of their electrical characteristics, but also have inherent disadvantages due to the presence of their buried-oxide (BOX) layers. In this paper, focus was placed on drain electric flux passing via the BOX layer to the body region as an influence that induces disadvantages such as drain-induced barrier lowering in SOI MOSFETs. The electric flux in the BOX layer was visualized using stream functions, and was quantitatively evaluated for the first time ever. The results showed the dependence of electric flux on relative permittivity and the BOX layer thickness. These outcomes confirmed that the subthreshold slope (SS) in short-channel SOI MOSFETs is affected strongly by electric flux detouring via the BOX layer, and the compact model of the enhancement of SSs due to the flux is proposed.

Magneto-transport in corrugated quantum wires

Abstract We study the low-temperature magneto-resistance of split-gate corrugated wires, in which the application of a suitable gate voltage leads to the formation of an array of coupled dots. At magnetic fields where the cyclotron orbit is comparable to the size of the individual dots, a series of striking peaks is observed in the magneto-resistance. A simple geometric analysis suggests that the peaks arise from a commensurate focusing effect, involving only backscattered orbits within the array. This result is consistent with the behavior found in studies of individual quantum dots, in which the connection between conductance and backscattered orbits has recently been emphasized.

In-depth profiling of electron trap states in silicon-on-insulator layers and local mechanical stress near the silicon-on-insulator/buried oxide interface in separation-by-implanted-oxygen wafers

In-depth profiling of electron trap states in silicon-on-insulator (SOI) layers of separation-by-implanted-oxygen (SIMOX) wafers was carried out using the drain current-gate voltage characteristics of metal-oxide-semiconductor field-effect transistors (MOSFETs) with different SOI thicknesses, and the density of electron trap states in a gate oxide (GOX) layer thermally grown on them was measured using the gate tunneling current-gate voltage characteristics of MOSFETs. It was found that in-depth profiles of electron trap states in SOI layers have a broad peak at around 25 nm from the SOI/buried oxide (BOX) interface, and that the density of electron trap states in a GOX layer grown on the 25-nm-thick SOI layer reaches a maximum there. A morphology study using Auger electron spectroscopy and Raman spectroscopic study revealed a correlation among the density of trap states in an SOI layer, roughness, and local mechanical stress near the SOI/BOX interface. This correlation is understood to imply that local me...