Toru Toyabe

A numerical model of avalanche breakdown in MOSFET's

An accurate numerical model of avalanche breakdown in MOSFETs is presented. Features of this model are a) use of an accurate electric-field distribution calculated by a two-dimensional numerical analysis, b) introduction of multiplication factors for a high-field path and the channel current path, and c) incorporation of the feedback effect of the excess substrate current induced by impact ionization into the two-dimensional calculation. This model is applied to normal breakdown observed in p-MOSFETs and to negative-resistance breakdown (snap-back or switchback breakdown) observed in short-channel n-MOSFETs. Excess substrate current generated from channel current by impact ionization causes a significant voltage drop across the substrate resistance in short-channel n-MOSFETs. This voltage forward-biases the source-substrate junction and increases channel current causing a positive feedback effect. This results in a decrease of the breakdown voltage and leads to negative-resistance characteristics. Current-voltage characteristics calculated by the present model agree very well with experimental results. Another model, highly simplified and convenient for device design, is also presented. It predicts some advantages of p-MOSFETs over n-MOSFETs from the standpoint of avalanche breakdown voltage, particularly in the submicrometer channel-length range.

Submicrometer MOSFET structure for minimizing hot-carrier generation

This paper reports on investigation of channel hot-carrier generation for various device structures. The dependences of channel hot-carrier generation on MOSFET structure are characterized by measuring the gate current and the substrate current as low as on the order of 10-15A. The measured gate current due to hot-electron injection into the oxide is modeled numerically as thermionic emission from heated electron gas over the Si-SiO 2 energy barrier. The substrate current due to hot-hole injection into the substrate is also modeled analytically. On the basis of the experiments and analyses, two device structures are proposed for minimizing hot-carrier generation and associated problems in submicrometer MOSFET: a graded drain junction structure and an offset gate structure. The proposed device structures provide remarkable improvements, raising by 2 V the highest applicable voltages as limited by hot-electron injection, as well as raising by 1-3 V the drain sustaining voltages as determined by the substrate hot-hole current. The influence of electron-beam radiation on the gate oxide is also discussed in relation to the trapping of hot electrons.

Analytical models of threshold voltage and breakdown voltage of short-channel MOSFET's derived from two-dimensional analysis

Analytical models of threshold voltage and breakdown voltage of short-channel MOSFETs are derived from the combination of analytical consideration and two-dimensional numerical analysis. An approximate analytical solution for the surface potential is used to derive the threshold voltage, in contrast with the charge conservation approach which has been usually taken. It is shown that the surface potential depends exponentially on the distance from the drain, and this causes the threshold voltage to decrease exponentially with decreasing channel length. The analytical dependence of threshold voltage on device dimensions, doping, and operating conditions is verified by accurate two-dimensional calculations, and the accuracy of the model is attained by slight modification. The breakdown voltage of a short-channel n-MOSFET is lowered by a positive feedback effect of excess substrate current. From two-dimensional analysis of this mechanism, a simple expression of the breakdown voltage is derived. Using this model, the scaling down of MOSFETs is discussed. The simple models of threshold and breakdown voltage of short-channel MOSFETs are helpful both for circuit-oriented analysis and process diagnosis where statistical use of the model is often needed.

Three-dimensional device simulator Caddeth with highly convergent matrix solution algorithms

A practical three-dimensional device simulator CADDETH (Computer Aided Device DEsign in THree dimensions) has been developed. Matrix solution methods appropriate to three-dimensional analyses have been devised. A vectorization ratio of 97 percent has been attained through efficient use of S-810 super computer with vectorized coding, resulting in a computation speed 16 times greater than can he obtained with S-810 in scalar mode computation. Full avalanche breakdown of MOSFETs can be readily simulated with good convergence and good agreement with experimental results.

Analytical models of threshold voltage and breakdown voltage of short-channel MOSFETs derived from two-dimensional analysis

An approximate analytical solution for the surface potential is used to derive the threshold voltage. It is shown that the surface potential depends exponentially on the distance from the drain, and this causes the threshold voltage to decrease exponentially with decreasing channel length. The analytical dependence of threshold voltage on device dimensions, doping, and operating conditions is verified by accurate two-dimensional calculations, and the accuracy of the model is attained by slight modification. The breakdown voltage of a short-channel n-MOSFET is lowered by a positive feedback effect of excess substrate current. From two-dimensional analysis of this mechanism, a simple expression of the breakdown voltage is derived. Using this model, the scaling down of MOSFETs is discussed. The simple models of threshold and breakdown voltage of short-channel MOSFETs are helpful both for circuit-oriented analysis and process diagnosis where statistical use of the model is often needed.

Simulation of sub-0.1- mu m MOSFETs with completely suppressed short-channel effect

MOSFETs in the sub-0.1- mu m regime were investigated using a nonplanar device simulator CADDETH-NP. It was found that even in this regime, the short-channel effect can be suppressed in grooved gate MOSFETs because of the concave corner of the gate insulator. MOSFETs with a gate length of 0.05 mu m or less with no threshold voltage lowering can be made by optimizing the concave corner radius, junction depths, and channel doping.<<ETX>>

Origin of characteristics differences between top and bottom contact organic thin film transistors

The differences in drain current and drain voltage (Id-Vd) characteristics of top and bottom contact organic thin film transistors (OTFTs) are analyzed by an OTFT devices simulator, which makes it possible to derive Id-Vd characteristics, potential distribution, and hole concentration distribution by solving Poisson’s equation and current continuity equation. It is found that the intrinsic characteristics of top contact devices are superior to those of the bottom contact ones, which is usually believed to be due to poor contact characteristics and poor semiconductor quality of bottom contact OTFTs. The mechanism behind the intrinsic characteristics differences is the deficiency of carriers at the source-channel interface, resulting to a very high potential drop, which the bottom contact devices suffer more. Remarkable improvements in drain current are expected by only inserting high carrier concentration region around the source/drain contact area, which totally eliminates the potential drop.

A soft error rate model for MOS dynamic RAM's

A soft error rate analysis model for MOS dynamic RAMs is presented. The soft error rate can be quantitatively calculated by using a solution of the equations for diffusion and collection of alpha-particle-induced excess electrons and by combining a statistical treatment of alpha particle energy, incidence angles, and incidence positions with the noise charge calculation. The model is then applied to analyze a soft error experiment on 64-kbit dynamic RAMs. It is shown that soft error characteristics with regard to signal charge (critical charge), as well as alpha energy and incidence angle dependencies, can be definitely determined. The model can also be used to predict the location of soft errors in MOS dynamic RAMs.

Short-channel-effect-suppressed sub-0.1-/spl mu/m grooved-gate MOSFET's with W gate

Grooved-gate Si MOSFETs with tungsten gates are fabricated using conventional manufacturing technologies, and their short-channel-effect-free characteristics are verified down to a source and drain separation of around 0.1 /spl mu/m. Phase shift lithography followed by a side-wall oxide film formation technique achieves a spacing of less than 0.2 /spl mu/m between adjacent elevated polysilicons, subsequently resulting in a sub-0.1-/spl mu/m source and drain separation in the substrate. Short-channel effects, such as threshold voltage roll-off and punchthrough, are found to be completely suppressed. From device simulations, the potential barrier formed at each grooved-gate corner is considered to be responsible for the suppression of the short-channel effects. >

An analytical and experimental investigation of the cutoff frequency f/sub T/ of high-speed bipolar transistors

The effects of vertical and lateral structures on cutoff frequency and breakdown voltage are investigated for high-speed bipolar transistors. The cutoff frequencies are examined in the range from 2.5 to 80 GHz by analysis and from 3 to 20 GHz by experiment. To attain the maximum cutoff frequency, it is predicted that the collector width, the base width, and the collector concentration should be 0.12 mu m, 0.07 mu m, and 1.2*10/sup 16/ cm/sup -3/, respectively, and that in this scaled transistor, breakdown voltages, BV/sub CE0/ and BV/sub C8O/ should be reduced below 3 and 7.7 V respectively. >