T.W. MacElwee

Compact representation of temperature and power dependence of thermal resistance in Si, Inp and GaAs substrate devices using linear models

Abstract A general model for the dependence of integrated device thermal resistance on substrate backside temperature and power dissipation for Si, InP and GaAs substrates is derived by consideration of the role of temperature dependent thermal conductivity in each of these effects. Linearization of these model components is carried out to extract computationally simple expressions that retain very close agreement to the full equations. A parameter extraction and scaling procedure is developed which allows the linearized models to be used in a practical modeling environment. The performance of extracted and scaled model parameters in predicting thermal resistance is compared to measurements for InP substrate devices, and the agreement and predictions are found to be within 5% of measurements for two geometries, for power levels to 3 mW/μm 2 and over a 165 °C substrate temperature range. The InP device model is also implemented as a subcircuit in hspice using behavioral sources, and the results confirmed with circuit simulation.

Bias Stress Measurements on High Performance AlGaN/GaN HFET Devices

High performance AlGaN/GaN heterojunction field effect transistor (HFET) devices have been fabricated, using material grown by MBE on sapphire substrates. The Hall effect 2DEG sheet charge densities and mobilities were as high as 1.68 × 10 13 cm -2 and 1000 cm 2 /Vs respectively. Peak dc currents in excess of 1 A/mm, with transconductances in excess of 220 mS/mm were common. f T and f max scaled linearly with the inverse of the gate length, with maximum values of 39 and 80 GHz recorded for T-gates of length 0.3 μm. The devices with optically defined gates were stressed at V DS = 10 V and V G = 1 V. for times up to 5000 s. The stress decreased both f T and f max , but this degradation mostly recovered after a few days. In contrast, the gate leakage current improved (decreased) with stressing, but did not return to the initial undesirable levels. Thus, we found that electrical bias stressing can have a positive effect on some of the characteristics of our devices.

Short-channel effects on MOSFET subthreshold swing

Abstract It is shown both experimentally and via MINIMOS simulation that the subthreshold swing S = ∂V G ∂ log 10 I D in a MOSFET may decrease significantly as gate length LG is reduced before increasing catastrophically when LG becomes so short that punchthrough current flows. The effect is largest in devices with lightly doped substrates, deep source/drain junctions, and heavy threshold adjust implants operated at high drain bias. An explanation for the effect is provided in terms of sharing of the depletion region charge between gate and drain.

Compact, netlist-based representation of thermal transient coupling using controlled sources

A compact, efficient electrical dual-circuit topology for the representation of transient thermal coupling is presented. Based on controlled sources, the method allows an arbitrary level of complexity to be used for each self and coupled response. Two possible variations on the circuit form, and the resulting requirements for model extraction, are developed. The method is applied to the modeling of transient thermal self-heating and coupling data for a pair of thermal sources representative of integrated device structures in semi-infinite homogeneous as well as trench-isolated substrates.

Growth and characterisation of high electron mobility transistors on 4H-SiC by ammonia molecular beam epitaxy

The growth of GaN/AIGaN high electron mobility transistor structures (HEMT) on 4H-SiC by ammonia molecular beam epitaxy (a-MBE) is reported. Structures were grown using a magnetron sputter epitaxy deposited AlN buffer layer prior to the MBE growth of a carbon-doped insulating GaN isolation layer, undoped GaN channel layer and AIGaN cap layer. No ex-situ or in-situ high temperature pre-treatment of the SiC substrate was used. The electrical characteristics of the layers was excellent with RT mobilities of >1100 cm 2 /Vs for a sheet carrier density of >1 x 10 13 cm -2 . 2 HEMTs fabricated from layers gave an f t and f max of 36 and 80 GHz, respectively with a maximum saturated drain current of 450 mA/mm and transconductance of 160 mS/mm for a gate length of 0.3 μm.

Growth of GaN/AlGaN HFETs on SiC substrates with optimized electrical characteristics using the ammonia-MBE technique

Optimization of the electrical characteristics of GaN/AlGaN HFETs grown on SiC substrates by ammonia-MBE is reported. By optimizing the growth conditions, GaN/AlGaN HFETs with room temperature mobilities of ∼1000 cm 2 /Vs and electron sheet densities of up to 1.9 x 10 13 cm -2 have been grown on SiC substrates with good reproducibility. These characteristics are comparable to the best characteristics of the GaN/AlGaN HFETs grown on sapphire. Devices fabricated from these optimized HFET layers showed excellent characteristics, e.g. maximum drain current density of 1.3 A/mm, f T of 70 GHz, f MAX of 130 GHz were measured for devices with 0.25 μm gate length and 100 μm gate width.

Formation of SiC for Microelectronic Applications by C Implantation into Doped a-Si

Heterojunction diodes have been formed by high-dose C implantation into thin n+ amorphous Si layers deposited on lightly-doped p-type Si substrates. FTIR and ellipsometry both indicate the conversion of the implanted layer to SiC following rapid thermal annealing at or above 1050°C. Resistivities as low as 300 mΩcm were obtained after RTA for SiC films over oxide. Diode J-V characteristics suggest the presence of a large depletion region recombination current component.