David J. Walkey

Equivalent circuit modeling of static substrate thermal coupling using VCVS representation

A new method is described which allows substrate thermal coupling between active devices to be accurately represented in a circuit simulation environment. The method, based on a substrate thermal equivalent circuit containing resistors and voltage-controlled voltage sources, allows for exact representation of substrate thermal coupling at any number of evaluation points. The topology of the equivalent circuit and derivation of its coefficients is described, and application of the technique to inter- and intradevice thermal effects is illustrated. The method is applied with a simple self-heating compact model representation to a measured GaAs device characteristic exhibiting gain collapse, and is found to accurately predict electrothermal behavior.

Modeling thermal resistance in trench-isolated bipolar technologies including trench heat flow

Abstract Heat flow in short emitter length bipolar devices in trench-isolated technologies is investigated through three-dimensional numerical thermal simulation, and thermal conduction through the trench walls is shown to be important for these structures. A new model is presented which predicts the thermal resistance of bipolar transistors in trench-isolated technologies down to emitter lengths of 1.2 μm. The effect of the parasitic thermal path introduced by emitter metal is also included in the new model. The prediction of this model is compared to numerical simulation and measurement, and found to be in excellent agreement.

Physical modeling of lateral scaling in bipolar transistors

The dependence of important transistor characteristics, such as transit frequency, on emitter width and length is modeled on a physical basis. Closed-form explicit analytical equations are derived for modeling the emitter size dependence of the low-current minority charge and transit time, the critical current indicating the onset of high injection in the collector, and the stored minority charge in the collector at high injection. These equations are suited for application in various compact transistor models such as the SPICE Gummel-Poon model (SGPM) as well as the advanced models HICUM and MEXTRAM. As demonstrated by two- and three-dimensional device simulation and measurements, combination of the derived equations with HICUM results in accurate prediction of the characteristics of transistors with variable emitter length and width. As a consequence, the new model makes the conventional transistor library unnecessary and offers bipolar circuit designers the flexibility to use the transistor size that fits the application best.

Simultaneous extraction of thermal and emitter series resistances in bipolar transistors

This paper describes a new method for simultaneous extraction of emitter and thermal resistance in bipolar transistors. The approach is verified using data generated by a compact model including self-heating and numerical simulation with lattice heating. Measured results are presented for the emitter and thermal resistances of self-aligned polysilicon devices and SiGe heterojunction devices.

Compact representation of temperature and power dependence of thermal resistance in Si, Inp and GaAs substrate devices using linear models

Abstract A general model for the dependence of integrated device thermal resistance on substrate backside temperature and power dissipation for Si, InP and GaAs substrates is derived by consideration of the role of temperature dependent thermal conductivity in each of these effects. Linearization of these model components is carried out to extract computationally simple expressions that retain very close agreement to the full equations. A parameter extraction and scaling procedure is developed which allows the linearized models to be used in a practical modeling environment. The performance of extracted and scaled model parameters in predicting thermal resistance is compared to measurements for InP substrate devices, and the agreement and predictions are found to be within 5% of measurements for two geometries, for power levels to 3 mW/μm 2 and over a 165 °C substrate temperature range. The InP device model is also implemented as a subcircuit in hspice using behavioral sources, and the results confirmed with circuit simulation.

A 3D thermal simulation tool for integrated devices-Atar

This paper presents a novel three-dimensional (3D) thermal simulation tool for semiconductor integrated devices. The simulator is used to automatically generate an accurate 3D physical model of the device to be simulated from layout information. The simulator produces an appropriate mesh of the device based on a rectangular block structure. The mesh is automatically created such that a fine mesh is produced around heat generation regions, but a moderate number of blocks are used for the entire device. This paper first confirms that the simulator produces an accurate solution to the nonlinear differential equation describing the heat flow. Then model generation from three example technologies (silicon trench, GaAs mesa structures, silicon on insulator) is presented. The potential of the simulator to quickly and easily explore the effect of layout and process variations is illustrated, with the simulation of a two-transistor GaAs power cell as a large example. The program incorporates a transient solver based on a transmission line matrix (TLM) implementation using a physical extraction of a resistance and capacitance network. The formulation allows for temperature dependent material parameters and a nonuniform time stepping. An example of a full transient solution of heat flow in a realistic Si trench device is presented.

Prediction of thermal resistance in trench isolated bipolar device structures

A model is proposed for predicting the thermal resistance of a trench isolated device structure. The model prediction for Nortels 0.35 /spl mu/m trench isolated 35 GHz f/sub T/ bipolar process is found to be within an average of 5% of measured values for three different emitter lengths over two wafers.

Transient 3D heat flow analysis for integrated circuit devices using the transmission line matrix method on a quad tree mesh

Abstract This paper presents a 3D transmission line matrix (TLM) implementation for the solution of transient heat flow in integrated semiconductor devices. The implementation uses a rectangular discontinuous mesh to allow for local mesh refinement. This approach is based on a quad tree meshing technique which can have a complex geometry using blocks of varying sizes. Each such block can have a maximum of two adjacent blocks on any vertical side and a maximum of four blocks on the top or bottom. The TLM implementation is based on a physical extraction of a resistance and capacitance network and then the creation of the appropriate TLM matrix. The formulation allows for temperature-dependent material parameters and a non-uniform time stepping. The simulator is first tested using a 2D example of a heat source in a rectangular region. Using this example the numerical error is determined and found to be less than 0.4%. Next, non-linearities are included, and a number of non-uniform time stepping algorithms are tested. Then, a 3D problem is also compared to an analytical solution and again the error is very small. Finally, an example of a full solution of heat flow in a realistic Si trench device is presented.

A simulation study of IC layout effects on thermal management of die attached GaAs ICs

Power management and thermal characterization of integrated power amplifiers is crucial to the development of a number of advanced technologies including portable wireless applications. Reduction and or optimization of device operating temperatures and thermal characteristics is needed to control temperature activated failure phenomena. This paper presents the use of PATRAN, a three-dimensional (3-D) model builder and finite element method (FEM) solver as means of understanding the heat flow in integrated devices and optimizing the layout for thermal operation. The approach taken is to assume a priori knowledge of the heat generation region and decouple the semiconductor transport equations. This allows for solution of the heat equation over a sufficiently large region to be correct. After verifying the correctness of the assumption of the device temperature being relatively insensitive to the depth, thickness and shape of the heat generation region, the optimization of heat spreaders in a GaAs HBT process is presented. This optimization is performed as an example of how both the maximum temperature and temperature variation across the emitter can reduced by careful design of the emitter metallization. Finally, the use of PATRAN is presented for extracting a three resistor thermal model for two devices in close proximity.

A thermal design methodology for multifinger bipolar transistor structures

A technique is presented that allows the increase in maximum temperature rise due to thermal coupling in multifinger structures to be predicted for a wide range of finger lengths and spacings by reference to a single, normalized characteristic. Application of this approach to the design of thermal resistance in multifinger structures results in a fast and straightforward method for generating families of structures that meet given power and temperature criteria without thermal simulation-based optimization. The usefulness of this approach is illustrated through solution of a practical design problem, and the accuracy of the method is verified by comparison with the final solutions to numerical simulation.