Tadahiro Matsuzaki

54.1: A Low-Power SOG LCD with Integrated DACs and a DC-DC Converter for Mobile Applications

A low-power 262k-color SOG (System-On-Glass) LCD has been developed for mobile applications. It is integrated with a DC-DC converter and driver circuits that contain 6- bit DACs, and it consumes less than 5 mW in operations with a single voltage power supply of 2.5 V.

A 470 × 235-ppi poly-Si TFT-LCD for high-resolution 2-D and 3-D autostereoscopic displays

— We have developed a 470 × 235-ppi poly-Si TFT-LCD with a novel pixel arrangement, called HDDP (horizontally double-density pixels), for high-resolution 2-D and 3-D autostereoscopic displays. 3-D image quality is especially high in a lenticular-lens-equipped 3-D mode because both the horizontal and vertical resolutions are high, and because these resolutions are equal. 3-D and 2-D images can be displayed simultaneously in the same picture. In addition, 3-D images can be displayed anywhere and 2-D characters can be made to appear at different depths with perfect legibility. No switching of 2-D/3-D modes is necessary, and the designs thin and uncomplicated structure makes it especially suitable for mobile terminals.

24.4: A 510-Kb SOG-DRAM for Frame-Memory-Integrated Displays

A system-on-glass (SOG) DRAM intended for integrated frame-memories of 262k-color QCIF+ displays has been developed. An integrated codec circuit reduces the number of memory cells and layout area by a factor of 2/3. By combining the SOG-DRAM, which has a data retention time of over 16.6 ms, with an embedded controller that enables simultaneous access for writing and reading, a frame-memory has been created. The operation was verified by chip measurement and demonstration.

A 510-kb SOG-DRAM for mobile displays with embedded frame memories

— A system-on-glass (SOG) dynamic random access memory (DRAM), which enables the implementation of frame-memory-integrated displays, has been developed. A dynamic one-transistor-one-capacitor memory cell, which has a data retention time of over 16.6 msec, and a compression/decompression (CODEC) circuit were developed to reduce the layout area and power. The CODEC enables an 18-bit/pixel color display, while reducing the memory capacity from 18 to 12 bits/pixel. A frame-memory macro was created by combining the SOG-DRAM with an embedded controller that enables independent access for writing and reading. Its operation was verified by chip measurement and demonstration as a frame-memory operation of 262k-color QCIF+ displays. The work reported in this paper was the first step to creating a Zero-Chip Display with an integrated frame memory, and it proved the concept was feasible.