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Dive into the research topics where Hiroshi Hayama is active.

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Featured researches published by Hiroshi Hayama.


SID Symposium Digest of Technical Papers | 2001

35.3: A Black Stripe Driving Scheme for Displaying Motion Pictures on LCDs

Takashi Nose; M. Suzuki; Daigo Sasaki; Masao Imai; Hiroshi Hayama

A novel driving scheme that enables displaying motion-pictures on LCDs is proposed, and a prototype LCD has successfully been demonstrated with a fast response LC cell. In this driving scheme, scanning black stripes are inserted in displayed images so that impulsive emission like that of CRTs can be produced. It is found that the LCD has a markedly improved motion-image quality compared with conventional LCDs.


international solid-state circuits conference | 2000

A 20 Gb/s CMOS multi-channel transmitter and receiver chip set for ultra-high resolution digital display

Muneo Fukaishi; Kunio Nakamura; H. Heiuchi; Yoshinori Hirota; Youetsu Nakazawa; Hidenori Ikeno; Hiroshi Hayama; Michio Yotsuyanagi

The digital display interface for an ultra-high resolution flat panel (3200/spl times/2400-pixels) requires 16 Gb/s bandwidth; moreover, 20 Gb/s is required when using an 8B10B encoder to increase serial data transmission accuracy. Low power consumption and low cost are also essential for consumer applications. These requirements are supported by multi-channel transmission, such as four 5 Gb/s CMOS LSIs, which is an effective approach to achieving an aggregate bandwidth of 20 Gb/s. There are two system problems in developing a multi-channel transmitter (TX) and receiver (RX) LSIs. One is the phase difference between multiple chips due to the data skew caused by differences between transmission cable lengths. The other is the frequency difference between the TX and RX system clocks. In response to these problems, we have developed compensation technology featuring the use of an elastic buffer for both the phase and frequency differences. Moreover, to achieve 6 Gb/s operation, a self-alignment phase detector with parallel output for a high-speed clock and data recovery circuit (CDR) and a 500 MHz fully pipelined 8B10B encoder are developed.


SID Symposium Digest of Technical Papers | 2002

29.2: Motion Picture Simulation for Designing High-Picture-Quality Hold-Type Displays

Daigo Sasaki; Masao Imai; Hiroshi Hayama

We have performed a novel motion picture simulation that can reproduce the perception of moving images on a screen of hold-type displays as still images. It can be used to evaluate motion picture quality quantitatively and to help improve the quality through optimization of the values of relevant parameters in hold-type displays like liquid crystal displays.


SID Symposium Digest of Technical Papers | 2004

54.1: A Low-Power SOG LCD with Integrated DACs and a DC-DC Converter for Mobile Applications

Yoshihiro Nonaka; Hiroshi Haga; Hiroshi Tsuchi; Youichi Kitagishi; Tadahiro Matsuzaki; Mitsuhiro Sugimoto; Hiroshi Hayama; Hideki Asada

A low-power 262k-color SOG (System-On-Glass) LCD has been developed for mobile applications. It is integrated with a DC-DC converter and driver circuits that contain 6- bit DACs, and it consumes less than 5 mW in operations with a single voltage power supply of 2.5 V.


SID Symposium Digest of Technical Papers | 2000

12.3: A New Low-Power TFT-LCD Driver for Portable Devices

Hiroshi Tsuchi; Naoyasu Ikeda; Hiroshi Hayama; K. Kitamura

In this paper, we describe a new low-power data-line driver for TFT-LCDs for portable devices. The driver contains newly-developed output buffers with low static current in place of operational amplifiers in a conventional driver. The new driver test-IC achieves about 85 % reduction in static current dissipation with a high output-voltage-resolution and a wide dynamic-output-range.


Journal of Applied Physics | 1998

Back-channel-oxidized a-Si:H thin-film transistors

Kazushige Takechi; Naoto Hirano; Hiroshi Hayama; Setsuo Kaneko

We have developed a back-channel-oxidized thin-film transistor (TFT) structure which does not require the conventional etching of the n+-a-Si:H layer from the channel region. Key processes in the fabrication of this structure are the deposition of a very thin (less than 10 nm) n+-a-Si:H layer with low resistivity (∼50 Ω cm), and an oxygen plasma treatment to change the n+-a-Si:H layer above the channel region into dielectric oxide. With a thin (∼50 nm) a-Si:H layer, the back-channel-oxidized TFT structure makes it possible to obtain much better “ON” characteristics than are obtained with conventional channel-etched TFTs. To gain insight into the underlying physical mechanism we investigated the back-channel electrical characteristics of both types of TFTs as a function of temperature, and found that back-channel-oxidized TFTs had much better back-channel characteristics than channel-etched TFTs, which is due to a lower density of back-channel interface states.


SID Symposium Digest of Technical Papers | 2002

16.2: A Parallel Digital‐Data‐Driver Architecture for Low‐Power Poly‐Si TFT‐LCDs

Hiroshi Haga; Hiroshi Tsuchi; Katsumi Abe; Naoyasu Ikeda; Hideki Asada; Hiroshi Hayama; Kunihiro Shiota; Naruaki Takada

A parallel digital-data-driver architecture has been developed to reduce power consumption in low-temperature poly-Si TFT-LCDs. It features low-power 3V-interface level shifters and 198 serial/parallel converters driven in parallel at a clock frequency of 62.5 kHz. Total power consumption in a 2.4-in., 41K(176 × 234)-pixel TFT-LCD with integrated 6b DACs is 12 mW at a 30-Hz frame frequency.


SID Symposium Digest of Technical Papers | 2003

51.1: A DC-DC Converter Circuit Integrated into a Poly-Si TFT LCD Containing a 6-bit DAC

Yoshihiro Nonaka; Hiroshi Tsuchi; Hiroshi Haga; Hideki Asada; Hiroshi Hayama; Naruaki Takada; Kenji Sera; Hiroyuki Uchida

A DC-DC converter composed of charge pumps and regulators has been integrated into a poly-Si TFT LCD that also contains a 6-bit DAC. It has the ability to supply regulated voltages to the 6-bit DAC and to the LCDs gate driver circuit.


international electron devices meeting | 1984

Promissing new fabrication process developed for stacked LSI's

Masaaki Yasumoto; Hiroshi Hayama; Tadayoshi Enomoto

A stacked CMOS LSI fabrication process has been developed for the purpose of realizing a short fabrication turn-around time, high fabrication yield and high integration density. This process consists of, in addition to the conventional LSI process, fabrication of vertical interconnections, surface planarization and thermal compression to obtain electrical interconnections between 2 layers. A 2-layer, bulk/CMOS ring oscillator consisting of p-channel MOSFETs on the upper layer and n-channel MOSFETs on the lower layer has been made using this new fabrication process. It has 31 bulk/CMOS inverter stages, each of which contains a single Au vertical interconnection with area of 10 × 10 µm2. A typical propagation delay time per stage for this device is measured to be 1.86 nsec at a supply voltage of 5 V.


SID Symposium Digest of Technical Papers | 1998

20.2: A Simple Reflective TFT‐LCD Fabrication Using Four Photomask Processes

Y. Yamaguichi; Hiroshi Kanoh; M. Mukainari; Hidenori Ikeno; Naoyasu Ikeda; Hiroshi Hayama

To reduce the production cost of reflective TFT-LCDs, we have developed a method of fabricating TFT-LCDS that is comprised of only four photo mask processes. Experimental black and white reflective LCDs fabricated with this method exhibit a lightness (L*) of 83, and no image parallax.

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