Tadanobu Toba

Impact of Scaling on Neutron-Induced Soft Error in SRAMs From a 250 nm to a 22 nm Design Rule

Trends in terrestrial neutron-induced soft-error in SRAMs from a 250 nm to a 22 nm process are reviewed and predicted using the Monte-Carlo simulator CORIMS, which is validated to have less than 20% variations from experimental soft-error data on 180-130 nm SRAMs in a wide variety of neutron fields like field tests at low and high altitudes and accelerator tests in LANSCE, TSL, and CYRIC. The following results are obtained: 1) Soft-error rates per device in SRAMs will increase x6-7 from 130 nm to 22 nm process; 2) As SRAM is scaled down to a smaller size, soft-error rate is dominated more significantly by low-energy neutrons (<; 10 MeV); and 3) The area affected by one nuclear reaction spreads over 1 M bits and bit multiplicity of multi-cell upset become as high as 100 bits and more.

Quantification and mitigation strategies of neutron induced soft-errors in CMOS devices and components

As semiconductor device scaling is on-going far below 100nm design rule, terrestrial neutron-induced soft-error typically in SRAMs is predicted to be worsen furthermore. Moreover, novel failure modes that may be more serious than those in memory soft-error are recently being reported. Therefore, necessity of implementing mitigation techniques is rapidly growing at the design phase, together with development of advanced detection and quantification techniques. The most advanced such techniques are reviewed and discussed.

Fault-based reliable design-on-upper-bound of electronic systems for terrestrial radiation including muons, electrons, protons and low energy neutrons

In-depth study on environmental radiation spectra of neutrons, protons, muons, electrons, gamma rays are carried out. Soft-error rates in 130nm SRAMs are estimated based on the survey results with the following conclusions: (1) Charge deposition by muons is relatively high when the muons penetrate p-wells in SRAMs, suggesting current devices have been already affected if the critical charge is below 1fC. (2) Electrons and gamma rays may have certain impacts when the critical charge reduces as low as 0.05fC, suggesting CMOS devices will be safe for at least near future against soft error by electrons and gamma rays. (3) Soft error rates due to both muons and electrons drastically increase as critical charge reduced below certain threshold values.

Novel SER standards: Backgrounds and methodologies

Standard methods to quantify SER susceptibility in memory devices have been established during 2000–2008. JESD89A issued in 2006 covers a wide variety of test methods for terrestrial neutrons and alpha particles. Spallation and (quasi-) monoenergetic neutron tests are among the best options for the SER tests. The methods, however, are being recognized as getting more inaccurate as device scaling proceeds. SER in logic devices is also getting more serious so that standard testing methods have to be established for logic devices. The new standards may include strategies for mitigation of SERs as well. The backgrounds and methodologies to promote new SER standards for device, chip, board layers are discussed in the present paper.

Evaluation Technique for Soft-Error Rate in Terrestrial Environment Utilizing Low-Energy Neutron Irradiation

Technology scaling of semiconductor devices improves circuit performance but at the same time degrades a radiation-induced soft-error tolerance. The measurement of soft-error tolerance of devices is one of key technologies to guarantee quality reliability. The conventional measurement methods require high-energy neutron beam. In this paper, we propose a method to measure soft-error rate in terrestrial environment irradiating with a low-energy neutron beam. Our proposed method requires low-energy neutron beam whose energy is less than 40MeV and the measurement cost can be reduced comparing the conventional methods. Our proposed method is applied to FPGAs fabricated in 90nm, 65nm, 40nm, and 28nm processes, and results of our proposed method are compared with those of conventional methods. The comparison results shows the accuracy of our proposed method is comparable with that of conventional ones for the CRAMs of FPGAs fabricated in processes less than 40 nm. Therefore, measurement cost reduction can be achieved with our proposed low-energy neutron method.

The Network Performance Analysis Platform and Its Application to Network Buffer Evaluation of the Embedded System

In this work, a network simulator is developed to predict the amount of hardware resources required for an embedded large-scale data processing system. It is difficult to simulate with the existing hardware simulator because the calculation time of processors lasts several days. This large time-consumption is caused by the fact that the processor module is made up of many components like CPU cores and shared buses. The target of this work is to complete the transmission simulation with one million packets in six hours. To reduce the analysis time, we focused on the shared bus of the processor and found that it is possible to estimate the amount of network buffer usage in a congestion state of packets in the shared bus. We have developed a shared bus timing model for calculating the packet transmission capacity by using the parameters related to the CPU core bus access time of the processor. Thereby, its simulation throughput can be increased up to 13 thousand packets per minute. The simulation results show that one million packets could be completed in two and a half hours by using the proposed techniques and confirmed that the proposed simulator can be used to optimize a large-scale data processing system.

Evaluation of neutron-induced soft error effects on CPUs in automotive microcontrollers

In this study, four types of microcontrollers (MCUs) operating under actual operating conditions, in which MCUs are regularly reset, are irradiated with white and quasi-monoenergetic neutron beams using our newly developed dynamic irradiation test environment. The results of the irradiation tests have good agreement, and show that neutron-induced soft error rates of the MCUs are almost the same, and are within the range of 0.1 to 0.2 FIT. Using the acquired data, the correlation between the characteristics of the running software and the number of soft errors are also analyzed.