Hideki Osaka

High-speed, high-bandwidth DRAM memory bus with crosstalk transfer logic (XTL) interface

Crosstalk Transfer Logic (XTL) is a digital-signal interface that uses directional couplers to form parallel lines within a circuit board. An advantage of the XTL is that it provides a multi-drop and high-speed system that is a one-to-many connection that can be used as a memory bus. To evaluate the signal integrity of an XTL to be applied to a DRAM bus, a test chip and boards were developed. We describe the design of the bus and report the results of its evaluation in this paper. The test chip was designed using a 0.15-/spl mu/m CMOS process and it had a controllable offset of the hysteresis receiver. A folding coupler was applied to the motherboard to condense the wiring and to reduce the noise from adjacent signals. The mother-board had only two coupler layers, with a four-byte data width, and it was capable of having eight modules mounted on the bits. The experimental results showed that the WRITE and READ operation reached speeds of at least 500 Mbps when eight modules were mounted on the bus.

Time-domain analysis of the signal integrity of a 1-Gbps 4-module memory bus with a broadband ceramic directional coupler designed in the frequency domain

To make a 1 Gbps 4-module memory bus at low cost, we designed a ceramic directional coupler (CDC) in the frequency domain and confirmed the performance of the bus in the time domain. The specification for the CDC was designed by translating the time domain properties to the S-parameters. We have fabricated the CDCs and verified the design validity and the bus performance using a test board. The results indicate effectiveness of the design method of the CDC and a 1-Gbps 4-module memory bus performance for the bus using the CDCs.

Measurement techniques for on-chip power supply noise waveforms based on fluctuated sampling delays in inverter chain circuits

To evaluate an on-chip power supply noise waveforms for power integrity design, we have developed a technique for measuring on-chip voltage waveforms. To overcome trade-offs in voltage resolution and the measurable frequency band, we designed inverter chain circuits that change the lengths of series inverters: a short chain provides low frequency and high resolution, while a long chain provides high frequency and low resolution. We measured on-chip noise waveforms using a 90 nm CMOS test chip with a 50 -inverter chain circuit as small as 320 square micrometers, confirming that the circuit could achieve a voltage resolution of 1 mV and temporal resolution of 20 ps. The amplitude of the noise waveform generated by the noise source circuits is proportional to the activating ratio of the source, although resonance frequencies are virtually the same - 160 MHz - when the activating ratios change.

Chip-package-PCB co-simulation for power integrity design at the early design stage

We investigated a chip-package-PCB co-simulation method for power integrity design at the early design stage. Due to the number of design parameters that need to be surveyed to optimize power integrity at this stage, the method requires fast power integrity analysis and a convenient way to revise design parameters. By applying a PEEC method with different mesh sizes for each component and reducing the input cost for the power and ground plane layout, we can reduce simulation costs with permissible levels of simulation error.

Modeling of chip-package resonance in power distribution networks by an impulse response

This paper proposes a method for modeling chip-package resonance using impulse response. To extract chip and package electrical circuit parameters, we assume a circuit equivalent to the loop from the chip to the package decoupling capacitor as the RL-RC parallel circuit and convert it into an RLC parallel circuit. We apply this method to devise an electrical circuit model capable of expressing chip-package resonance with high accuracy, as confirmed by experimental results.

Low-cost, Low-noise Vref Design for High-speed DDR Memory Modules

This paper discusses new Vref designs for high-speed memory modules. Our designs include chip resistors in series with Vref traces that reduce the total noise. We confirmed reduced noise of half the original through experiments

Hybrid silicon and glass interposer for combined optical and memory system-in-package

This paper proposes a low-cost packaging configuration for a combined optical and memory system-in-package. The proposed hybrid silicon and glass configuration meets the wiring density required for HBM and high-frequency characteristics required for optical IC wiring. We also built and tested a wiring TEG to evaluate the high-frequency performance of 25 Gbps differential transmission wiring for optical ICs in the glass interposer region, thereby seeking to minimize losses and reduce power consumption. Experiments showed satisfactory transfer characteristics of □0.8 dB/cm.

Power distribution network design method based on frequency-dependent target impedance for jitter design of memory interface

This paper proposes a PDN design method using frequency-dependent target impedance considering frequency properties of jitter sensitivity of the IO buffer to power supply noise and switching current profile. We confirmed that this design and the resulting jitter of the I/O interface attributable to power supply noise meet the target value of less than 5 %UI.

Average transmission cross section of aperture arrays in electrically large complex enclosures

Analytical approximations for the average transmission cross sections of aperture arrays in thick conducting walls have been calculated, including square arrays of square apertures and rhombic arrays of hexagonal apertures. The equations can be used for estimating the shielding efficiency of practical conducting enclosure at high frequencies. The results are compared with numerical simulations. Some possible design guidelines based on the proposed equations are also discussed.

PCB trace modeling and equalizer design method for 10 Gbps backplane

This paper discusses accurate PCB modeling methods for 10 Gbps differential signal traces. We added two approaches to the conventional modeling method: (1) We simulated the glass cloth and epoxy distribution in the PCB dielectric to simulate common/differential mode conversion noise (SCD21). (2) We applied a frequency-dependent dielectric constant to the electromagnetic analysis model based on a Djordjevic-Sarkar model to introduce a frequency-dependent group delay. Applying these two additional modeling elements, we obtained accurate SCD21 and jitter properties consistent with measurement results. We also demonstrated an equalizer design based on the improved PCB model. By flattening the frequency dependence of the group delay as well as trace losses for the transmission paths, including the equalizer, by adjusting the properties of the peaking amplifier for the equalizer circuit, we reduced jitter by up to 10 ps for 10 Gbps signalling.