Tadeusz Kwasniewski

A 1.2 /spl mu/m CMOS implementation of a low-power 900-MHz mobile radio frequency synthesizer

A single-chip, low-power all CMOS PLL frequency synthesizer for digital mobile radio communication systems is presented. The design of PLL components: VCO, dual-modulus prescaler and phase-frequency detector are discussed. Novel circuit techniques and design methodology allow GHz frequency range operation, and result in good phase noise performance. The measured results of a monolithic 1.2 /spl mu/m CMOS PLL implementation indicate a frequency range of 800 to 900 MHz with -94 dBc/Hz phase noise at a 1 MHz carrier offset, and a power consumption of 18 mW at 5 volts.<<ETX>>

FIR filter optimization as preemphasis of high-speed backplane data transmission

FIR filter preemphasis has been used to counteract intersymbol interference (ISI) in high-speed backplane data transmission. Backplane channel characteristics are first analyzed. It is found that channel group delay distortion is also a major ISI contributor in addition to amplitude attenuation. A MATLAB program is then described for optimization of the FIR filter under the LMS criterion. Both symbol-spaced FIR (SSF) and fractionally-spaced FIR (FSF) are comparatively studied at different data rates. The determination of tap number and preference of FSF to SSF are discussed.

Challenges in the Design of Next Generation WLAN Terminals

In recent years advancements in the field of wireless communications have generated interest in the deployment of multiple antenna systems (MIMO) for mobile terminals. Next generation wireless local area networks (WLANs) standards such as IEEE 8(12.1 In are based on MIMO and will be operating at bit rates above 200 Mbps. The physical layer (PHY) of the 802.11n supports multiple modulation schemes, multiple antennas configuration, variable code rate and multiple space-time coding schemes. Receiver architecture should be able to support all these features preferably in a single reconfigurable architecture. Besides all these requirements need to be designed and implemented under the strict low power and low complexity (low area) design criteria.

Design Considerations for a Direct RF Sampling Mixer

This brief presents a detailed time-domain and frequency-domain analysis of a direct RF sampling mixer. Design considerations such as incomplete charge sharing and large signal nonlinearity are addressed. An accurate frequency-domain transfer function is derived. Estimation of noise figure is given. The analysis applies to the design of sub-sampling mixers that have become important for software-defined radio and analog-to-digital converter.

FIR filter optimization using bit-edge equalization in high-speed backplane data transmission

A unique bit-edge equalization (BEE) method for mitigating intersymbol interference (ISI) in high-speed backplane applications is presented. Using a least-mean-square (LMS) adaptive algorithm as a receiver (RX) error convergence engine, the proposed BEE method aims to optimize the bit-edge amplitudes by equalizing only the edges of data bits with an adjustment of the sampling points where the error information is collected. This adjustment of sampling points in turn changes the error information and affects filter coefficients for pulse amplitude modulation. As a result, the channels far-end 3-level bit-edge eye diagrams can be optimized. This proposed BEE method employs transmitter (TX) pre-coding in conjunction with TX pre-emphasis using a symbol-spaced FIR (SSF) filter. In this work, a detailed analytical comparison of the proposed BEE transceiver architecture with the conventional NRZ bit-centre equalization (BCE) and duobinary transceiver architectures is presented. The simulation results demonstrate that at 10+Gbps data rates, the proposed BEE is the most effective method for mitigating ISI in relatively high-loss channels.

Analysis, Optimization, and Design of 2–2.8

The 2-2.8 μm vertically stacked multiple-junction PIN GalnAsSb/GaSb photodetectors are analyzed, optimized, and designed based on an improved general mode to predict the optimal performance of PIN infrared photodetectors arising from nonequilibrium carrier generation, diffusion, and recombination theory. Optimal thickness of intrinsic absorption region (Wopt), response quantum efficiency (RQE), detectivity (D*), and -3-dB cutoff frequency (f_{_3dB}) are calculated and optimized for a 2-2.8 μm room-temperature high-frequency operation. Ways to achieve optimal performance in practice, material, and device structures are proposed. The optimized vertically stacked multiple-junction PIN GalnAsSb/GaSb photodetector structure shows a D* of (1.6-1.9) × 10¹² cm· Hz^1/2/W,an RQE of 52%-69%, and a f_{- 3 dB} ≫ 20 GHz with W_opt = 3 μm and junction number K = 5, effective illumination area A_d = 1000 μm², and reverse bias voltage V_RB = 0.5 V. The proposed general model is validated by simulation and measurement data of fabricated single-junction detectors.

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This paper presents an improved bit-edge equalization (BEE) method for mitigating intersymbol interference (ISI) in high-speed backplane applications. Using a least-mean-square (LMS) adaptive algorithm as a receiver (RX) error convergence engine, the proposed BEE method is based on equalizing only the edges of data bits with an adjustment of LMS error derivation points, which in turn changes the error information and affects filter coefficients for pulse amplitude modulation. As a result, the received channel far-end 3-level bit-edge eye diagrams can be optimized. This proposed BEE method employs a conventional symbol-spaced FIR (SSF) filter as transmitter (TX) pre-emphasis for bit-edge equalization. With TX data pre-coding, the received channel far-end 3-level signal to 2-level binary decoding only depends on the current received bit. No error propagation occurs. In this work, the proposed BEE method is compared with the bit-center equalization (BCE) method and duobinary signaling method by applying the adjustment of LMS error derivation points in all these methods. A typical Tyco 34-inch FR4 backplane channel is used as the comparison benchmark. A Matlab script based link simulation tool is used to evaluate the link performance. The simulation results demonstrate that the proposed BEE method is the most effective for mitigating ISI in relatively high-loss channels.

Stacked Multiple-Junction PIN GaInAsSb/GaSb Photodetectors for Future O/E Interconnections

This paper presents the behavioral implementation of jitter tolerance test benches for digital clock and data recovery circuits using Verilog-A. First, we encode a variable-length pseudo-random bit sequence (PRBS) generator. Such circuits are widely used to generate test data for a variety of circuits and systems. Using this PRBS generator, we set up a test bench for the evaluation of jitter tolerance. A novel simulation methodology is described that modulates the amplitude and frequency of the jitter sinusoid iteratively to find the jitter tolerance. We conclude with a comparison of jitter tolerance simulation results, computed using various PRBS lengths, for the data recovery circuit under test

ISI mitigation using bit-edge equalization in high-speed backplane data transmission

Event driven phase noise simulation and modeling of an ADPLL by SystemVerilog is presented in this paper. It uses the simple Stochastic Voss-McCartney algorithm to generate the pink noise so that the 1/f phase noise effect can be easily modeled. Since the event driven simulation is extremely fast compared to the circuit level simulation, it allows circuit designers to explore different ADPLL architectures at the early stage without going through the time-consuming circuit level simulation. Pure SystemVerilog implementation also makes it possible to simulate the phase noise effect of the ADPLL efficiently in a large SOC system.

Behavioral test benches for digital clock and data recovery circuits using Verilog-A

Two different hardware structures of a sign-sign block least-mean-square (LMS) algorithm for an adaptive pre-emphasis in a backplane transceiver have been implemented in Verilog targeting the TSMC 0.18 /spl mu/m CMOS technology. Functional models and Matlab code have been developed to simulate a transceiver system for both structures. A pulse amplitude modulated four-level (4-PAM) signaling technique is used in the Matlab simulation. Results show that the proposed parallel adaptation engine is four times faster than the published round-robin adaptation engine in terms of coefficient update rate with comparable hardware. Both circuits prove that digital CMOSP18 standard cells can be used directly to achieve 625 MHz timing constraints. A custom circuit is not needed to implement the digital adaptation algorithm for the analog adaptive pre-emphasis up to 625 MHz.