Dianyong Chen

Design Considerations for a Direct RF Sampling Mixer

This brief presents a detailed time-domain and frequency-domain analysis of a direct RF sampling mixer. Design considerations such as incomplete charge sharing and large signal nonlinearity are addressed. An accurate frequency-domain transfer function is derived. Estimation of noise figure is given. The analysis applies to the design of sub-sampling mixers that have become important for software-defined radio and analog-to-digital converter.

A reduced power 6-tap pre-emphasis for 10GB/S backplane communications

Pre-emphasis is often employed at the transmitter side to counteract the inter symbol interface (ISI) in high-speed data communications. Traditional pre-emphasis drivers, implemented in CML, use one pair of CMOS transistors as the output stage. To design a pre-emphasis for different channels or the same channel using different type of equalizer requires a wide range of current for the same tap. The challenge for traditional circuits is how to choose the sizes for these transistors. To meet this challenge, this paper presents a lower 6-tap pre-emphasis with several pairs of transistors at output stage to solve this issue. The simulation shows the eye diagram for the same channel improved vertical 8% and horizontal 5%. The pre-emphasis consumes only 57.7 mW with a total of 6 tabs.

A programmable pre-cursor ISI equalization circuit for high-speed serial link over highly lossy backplane channel

This paper presents a programmable pre-cursor ISI equalization circuit for high-speed serial data transmission over highly lossy electrical backplane channels. Although decision-feedback-equalizer (DFE) provides an effective way to compensate various channel impairments, such as frequency dependent loss, dispersion and reflections in the legacy backplane environment, for high-speed, highly lossy band-limited channel, the pre-cursor inter-symbol interference (ISI) is still a significant problem for channel equalization. A programmable pre-cursor ISI equalizer combined with a 3-tap DFE is implemented to work at 10-Gb/s and compensate the channel loss of −20 dB. The results show it outperform a traditional 5-tap DFE.

Optimized biasing technique for high-speed digital circuits with advanced CMOS nanotechnology

This paper presents a biasing optimization technique for high-speed digital circuits design with advanced CMOS nanotechnology. Modern CMOS nanotechnology introduces several new problems in high-speed circuits design. As the fastest signal frequency components approach the peak transition frequency of the MOSFET, which depends heavily on the biasing voltage, the optimized biasing techniques become very important in high-speed circuits. Many trade-offs in the high-speed circuits need to be considered, and either power or headroom may be traded for higher speed. The optimized biasing technique is thoroughly analyzed first in this paper, and a typical high-speed CML circuit is designed based on this technique.

A new storage material for rewritable blue-light DVD

A category of new photochromatic storage material has been found suitable for rewritable digital video disc (DVD). The ratio of transmissivity before and after the write-in process is 3:1 at /spl lambda/=450 nm (blue) and 2:7 at /spl lambda/=650 nm (red), with a transition time of 2-3 ns. The number of write-erase cycles is about 1,000.

Analyze and design 10-GHz 0.8-V DD -117dBc/Hz quadrature LC-VCO in 120nm CMOS technology

A low supply voltage low phase noise 10-GHz CMOS quadrature LC-VCO (LC-QVCO) is systematically analyzed and designed for low power applications in wireline and wireless communication systems. Using a semi-empirical model, the impacts on VCO oscillation magnitude, loaded quality factor (Qloaded), and oscillation frequency from the parasitic components of passive and active devices are formulated in simple mathematic equations. The predicted VCO performance and the widely used linear model of LC-QVCO are verified by timedomain simulations, frequency-domain total loop gain analysis, and measurement data based on a 120nm RF CMOS technology.

A monolithic high modulation efficiency CMOS laser diode / modulator driver

A high modulation efficiency laser diode/modulator driver (LDD/MD) is designed for low-cost optical access networks using shunt peaking active inductors and direct-coupled topology to boost the bandwidth, to improve modulation efficiency, and to reduce the silicon area. It provides a maximum modulation current of 74mA or a maximum modulation voltage of 3.9V through an equivalent 50Ω load. Fully-open optical eye diagrams were observed at bit rate up to 1.25-Gb/s when it used as a LDD or a MD. The maximum RMS jitter is 38ps. The 0.4mm2 chip consumes only 470mW in 5V 0.6µm standard CMOS.

Decision-Feedback-Equalizer for 10-Gb/s backplane transceivers for highly lossy 56-inch channels

This paper presents a decision-feedback-equalizer for 10-Gb/s backplane transceivers for highly lossy channels. Forward equalization is not used in order to avoid noise enhancement. The sampling phase is optimized to achieve maximum signal-to-noise-ratio at the sampling instants. The coefficients of feedback finite-impulse-response filter and the gain of variable-gain-amplifier are obtained automatically by adaptive circuits. The vertical eye opening is almost doubled compared with a conventional decision-feedback-equalizer for a 56-inch channel with heavy loss more than -6.5 dB/GHz. The DFE is implemented in 0.13-mum IBM RF CMOS technologies. Results show an 8-tap DFE can open the highly blurred eye diagram, while a 12-tap conventional DFE can not open it. A 10-tap DFE yields a very clear eye diagram for PRBS-9 test patterns.

A novel CMOS edge equalizer for 10-GB/S highly lossy backplane

This paper presents a novel CMOS edge equalizer for 10-Gb/s transceivers for backplane channels with high loss. The equalizer reduces ISI at edges and ISI at data centers simultaneously without incurring multilevel detection. Unlike conventional edge equalizer that recovers data from current sample and previous sample, this equalizer recovers data only from current sample so that error propagation is avoided. It requires much less high-frequency boost while maintaining the amenity for CMOS implementation of conventional CMOS feed-forward-equalizer. The equalizer is implemented in TSMC 90-nm CMOS technologies. Comparison shows for highly lossy backplane applications, it is superior to decision-feed-back-equalizer, linear-feed-forward-equalizer, and conventional edge equalizer.

An improved simulation method for high-speed data transmission through electrical backplane

Wireline transceivers for high-speed data transmission through backplane and ethernet cables are important applications for microelectronic and nanoelectronic CMOS technologies. Although many circuit simulators provide correct system-level and transistor-level simulations, they usually fail to give correct results for many highly lossy or/and highly dispersive channels. This paper discusses the advanced simulator that we developed. It can give correct simulation results for those channels. It can also process those channel model files to allow commercial circuit simulators to give correct results. This simulator when used together with commercial simulators gives correct system-level and transistor-level simulation results.