Tae-Kwang Jang

Analysis and Design of Voltage-Controlled Oscillator Based Analog-to-Digital Converter

A voltage-controlled oscillator (VCO) based analog-to-digital converter (ADC) is a time-based architecture with a first-order noise-shaping property, which can be implemented using a VCO and digital circuits. This paper analyzes the performance of VCO-based ADCs in the presence of nonidealities such as jitter, nonlinearity, mismatch, and the metastability of D flip-flops. Based on this analysis, design criteria for determining parameters for VCO-based ADCs are described. In addition, a digital calibration technique to enhance the spurious-free dynamic range degraded by the nonlinearity is also introduced. To verify the theoretical analysis, a prototype chip is implemented in a 0.13-¿m CMOS process. With a 500-MHz sampling frequency, the prototype achieves a signal-to-noise ratio ranging from 71.8 to 21.3 dB for an input bandwidth of 100 kHz-247 MHz, while dissipating 12.6 mW and occupying an area of 0.078 mm2.

A Time-Based Bandpass ADC Using Time-Interleaved Voltage-Controlled Oscillators

In this paper, a bandpass analog-to-digital converter (ADC) based on time-interleaved oversampled ADC is introduced. Unlike previous delta-sigma bandpass ADCs that require accurate digital-to-analog converters and high-speed analog circuits, the proposed architecture provides bandpass function by time-interleaving first-order voltage-controlled-oscillator (VCO)-based ADCs. The use of VCO-based ADC has the advantage that its resolution is determined by the time resolution rather than the voltage resolution, thus making it attractive for future low-voltage CMOS processes. The performance of the proposed ADC is theoretically analyzed and simulated in ideal condition, as well as in nonideal condition, in the presence of nonlinearity, sampling clock jitter, and mismatch.

21.5 A current-mode wireless power receiver with optimal resonant cycle tracking for implantable systems

Continuous health monitoring has become feasible, largely due to miniature implantable sensor systems such as [1]. To recharge batteries of such systems, wireless power transfer is a popular option since it is non-invasive. However, there are two main challenges: 1) strict safety regulations of incident power on human tissue; 2) small coil size for better biocompatibility. These issues reduce the received power at the coil, make it difficult to obtain sufficient power for implanted devices, and call for high power-efficiency (ηP)-transfer techniques, especially at very low received power levels.

A 110 nW Resistive Frequency Locked On-Chip Oscillator with 34.3 ppm/°C Temperature Stability for System-on-Chip Designs

This work presents a sub-μW on-chip oscillator for fully integrated system-on-chip designs. The proposed oscillator introduces a resistive frequency locked loop topology for accurate clock generation. In this topology, a switched-capacitor circuit is controlled by an internal voltage-controlled oscillator (VCO), and the equivalent resistance of this switched-capacitor is matched to a temperature-compensated on-chip resistor using an ultra-low power amplifier. This design yields a temperature-compensated frequency from the internal VCO. The approach eliminates the traditional comparator from the oscillation loop; this comparator typically consumes a significant portion of the total oscillator power and limits temperature stability in conventional RC relaxation oscillators due to its temperature-dependent delay. A test chip is fabricated in 0.18 μm CMOS that exhibits a temperature coefficient of 34.3 ppm/°C with long-term stability of less than 7 ppm (12 second integration time) while consuming 110 nW at 70.4 kHz. A radio transmitter circuit that uses the proposed oscillator as a baseband timing source is also presented to demonstrate a system-on-chip design using this oscillator.

A 23pW, 780ppm/°C resistor-less current reference using subthreshold MOSFETs

This paper proposes a MOSFET-only, 20pA, 780ppm/°C current reference that consumes 23pW. The ultra-low power circuit exploits subthreshold-biased MOSFETs and a complementary-to-absolute temperature (CTAT) gate voltage to compensate for temperature dependency. The design shows low supply voltage sensitivity of 0.58%/V and a load sensitivity of 0.25%/V.

A 5.58 nW Crystal Oscillator Using Pulsed Driver for Real-Time Clocks

A 5.58 nW real-time clock using a crystal oscillator is presented. In this circuit, the amplifier used in a traditional circuit is replaced with pulsed drivers. The pulse is generated with precise timing using a DLL. With this approach, an extremely low oscillation amplitude of 160 mV results in low-power operation. This low-amplitude oscillation is sustained robustly using additional supply voltages: a lower supply for the final drive stage and a higher supply used for pulses that drive the final drive stage, which ensures low ON-resistance necessary for reliable operation. The different supply levels are generated on-chip by a switched capacitor network (SCN) from a single supply. The circuit has been tested at different supply voltages and temperatures. It shows a minimum power consumption of 5.58 nW and power supply sensitivity of 30.3 ppm/V over supply voltage of 0.94-1.2 V, without degrading the crystals temperature dependency: between -20 °C and 80 °C. Moreover, its performance as a real-time clock has been verified by measurement of an Allan deviation of 1.16 × 10-8.

5.8 A 4.7nW 13.8ppm/°C self-biased wakeup timer using a switched-resistor scheme

Miniaturized computing platforms typically operate under restricted battery capacity due to their size [1]. Due to low duty cycles in many sensing applications, sleep-mode power can dominate the total energy budget. Wakeup timers are a key always-on component in such sleep modes and must therefore be designed with aggressive power consumption targets (e.g., <;10nW). Also, accurate timing generation is critical for peer-to-peer communication between sensor platforms [1]. Although a 32kHz crystal oscillator can provide low power [2] and accurate long-term stability, the requirement of an off-chip component complicates system integration for small wireless sensor nodes (WSNs).

A 0.004mm 2 250μW ΔΣ TDC with time-difference accumulator and a 0.012mm 2 2.5mW bang-bang digital PLL using PRNG for low-power SoC applications

As digital CMOS technology scales to 32nm and below, small and low-voltage clock and timing generators are in high demand to avoid complex analog operations and to meet stringent phase noise requirements. There have been sever- al approaches to convert analog systems to their digital counterparts and a high- resolution time-to-digital converter (TDC) is a key element for the digitalization of analog circuits. Recently TDCs using a noise shaping technique with oversampling have been introduced to improve resolution. However, they tend to be power hungry or require analog-intensive circuitry as they convert signals from the time domain to the voltage domain in order to perform arithmetic operations. A digital PLL (DPLL) is another crucial SoC component, and low-power area-efficient DPLLs are challenging to design. This paper presents a time-domain low-power ΔΣ TDC with a time-difference accumulator and an area-efficient, low-power, and fast-lock DPLL composed of a synthesizable bang-bang phase and frequency detector (BB-PFD), with a gain boosting mode and a pseudo-random number generator (PRNG).

A 99nW 70.4kHz resistive frequency locking on-chip oscillator with 27.4ppm/ºC temperature stability

We present a low power on-chip oscillator for system-on-chip designs. The oscillator introduces a resistive frequency locking loop topology where the equivalent resistance of a switched-capacitor is matched to a temperature-compensated resistor. The approach eliminates the traditional comparator from the oscillation loop, which consumes significant power and limits temperature stability in conventional relaxation oscillators. The oscillator is fabricated in 0.18μm CMOS and exhibits 27.4ppm/oC and <;7ppm long-term stability while consuming 99.4nW at 70.4 kHz.

A 0.026mm 2 5.3mW 32-to-2000MHz digital fractional-N phase locked-loop using a phase-interpolating phase-to-digital converter

Recent innovations in semiconductor processes have accelerated the transition from analog circuits to their digital counterparts, with digital PLLs (DPLLs) being an example of this trend [1]. All-digital or fully synthesizable approaches, which exploit the merits of advanced processes, suffer from poor noise performance and high power consumption [2]. On the other hand, hybrid approaches, which employ analog components such as digital-to-analog converters (DACs), digital-to-time converters, phase interpolators (PIs) and regulators, have the typical difficulties associated with analog circuits, such as low output resistance, small voltage headroom and large variation. In this paper, we propose a highly digital architecture for a DPLL - one which minimizes the design effort typically required for analog circuits. The power and area-consuming circuits in prior works are replaced by power and area-efficient circuits with competitive performance. For example, a conventional time-to-digital converter (TDC) usually occupies considerable chip area in order to maximize input dynamic range with precise resolution [1]. Instead, in this work, a time-windowed phase-to-digital converter using interpolated DCO phases as a phase reference is adopted. In addition, conventional synchronous counters in the feedback path drastically increase the power consumption. Furthermore, retiming of data from the TDC is unavoidable due to the meta-stability of the sampling flip-flops [1]. The proposed divider scheme, which is composed of a multi-modulus frequency divider and a dead-zone-free phase and frequency detector (PFD), eliminates the need for a synchronous counter and retiming circuits. A calibration-free ΔΣ modulator (DSM) noise canceller is also included.