Ki-Seok Chung

An algorithm for synthesis of system-level interface circuits

We describe an algorithm for the synthesis and optimization of interface circuits for embedded system components such as microprocessors, memory ASIC, and network subsystems with fixed interfaces. The algorithm accepts the timing characteristics of two system components as input, and generates a combinational interface (glue logic) circuit. The algorithm consists of two parts. In the first part, we determine the direct pin-to-pin connections in the interface circuit employing a 0/1 ILP formulation to minimize wiring area and dynamic power consumption. In the second part, we determine logic subcircuits in the interface circuit, utilizing the timing diagrams of the system components. The proposed algorithm has been implemented in a software package SYNTERFACE. Experimental results are presented to demonstrate the effectiveness of the algorithm.

Local transformation techniques for multi-level logic circuits utilizing circuit symmetries for power reduction

In this pap er, we present sever al optimization techniques for power reduction utilizing circuit symmetries. There are four kinds of symmetries that we dete ct in a given circuit implementation. First, we pr op ose an algorithm for dete cting the four different typ es ofsymmetries in a given circuit implementation of a Boole an function. Sever alre-synthesis techniques utilizing such symmetries are prop ose d. These techniques enable us to optimize power consumption and delay with no (or very little) ar ea overhead. We have carrie dout experiments on MCNC benchmark circuits to demonstrate the efficiency of the prop ose dtechniques. The aver age power reduction is 14% with little or none ar ea and/or delay overhead.

A stepwise refinement data path synthesis procedure for easy testability

This paper presents a new data path synthesis algorithm which takes into account simultaneously three important design criteria: testability, design area, and total execution time. We define a goodness measure on the testability of a circuit based on three rules of thumb introduced in prior work on synthesis for testability. We then develop a stepwise refinement synthesis algorithm which carries out the scheduling and allocation tasks in an integrated fashion. Experimental results for benchmark and other circuit examples show that we are able to enhance the testability of circuits with very little overheads on design area and execution time.<<ETX>>

G-vector: A New Model for Glitch Analysis in Logic Circuits

One of the major factors which contribute to the power consumption in CMOS combinational logic circuits is the switching activities in the circuits. Many of such switching activities are due to spurious pulses, called glitches. In this paper, we propose a new model for describing signals that contain glitches, called G-vector. Unlike the previous works in which their primary concern is modeling the propagation of glitches to count the number of glitches in the circuits, our G-vector provides a general, but effective model for generation, propagation and elimination of glitches, enabling us to not only count the number of glitches but also locate the glitches so that such information can be utilized by system tools for the reduction of the number of glitches in the circuits. We provide a set of experimental results to demonstrate the effectiveness of our model.

G-vector: a new model for glitch analysis

One of the major factors which contribute to the power consumption in CMOS combinational logic circuits is the switching activities in the circuits. Many of such switching activities are due to spurious pulses, called glitches. In this paper, we propose a new model for describing signals that contain glitches, called G-vector. Unlike the previous works in which their primary concern is modeling the propagation of glitches to count the number of glitches in the circuits, our G-vector provides a general, but effective model for generation, propagation and elimination of glitches, enabling us to not only count the number of glitches but also locate the glitches so that such information can be utilized by system tools for the reduction of the number of glitches in the circuits. We provide a set of experimental results to demonstrate the effectiveness of our model.

Synthesis and Optimization of Combinational Interface Circuits

We describe an algorithm for interface synthesis and optimization for embedded system components such as microprocessors, memory ASIC, and network subsystems. The algorithm accepts the timing characteristics of two chips as input, and generates a combinational interface circuitry to implement communication between them. The algorithm consists of two parts. In the first part, we determine the direct pin-to-pin connections employing a 0-1 ILP formulation to minimize wiring area and dynamic power consumption in the resulting interface circuit. In the second part, we use a novel encoding method to synthesize connections between chips which require additional gates in the interface circuit. Experiments show that our algorithm is very effective in practice.

A static estimation technique of power sensitivity in logic circuits

In this paper, we study a new problem of statically estimating the power sensitivity of a given logic circuit with respect to the primary inputs. The power sensitivity defines the characteristics of power dissipation due to changes in state of primary inputs. Consequently, estimating the power sensitivity among the inputs is essential not only to measure the power consumption of the circuit efficiently but also to provide potential opportunities of redesigning the circuit for low power. In this context, we propose a fast and reliable static estimation technique for power sensitivity based on a new concept calledpower equations, which are then collectively transformed into a table calledpower table. Experimental data on MCNC benchmark examples show that the proposed technique is useful and effective in estimating power consumption. In summary, the relative error for the estimation of maximum power consumption is 9.4\% with a huge speed-up in simulation.

Behavioral-level partitioning for low power design in control-dominated application

In this paper, we study the problem of behavioral-level partitioning for low power design. By behavioral-level partitioning, we mean a partitioning which is done at the behavioral description where scheduling and allocation have not been carried out. The motivation is that turning on/off individual operations cycle-by-cycle is very expensive, thereby we provide a partitioning solution so that all operations in the same partition can be controlled by the same gated clock signal. Our partitioning algorithm is specifically focused on the applications which contain many nested conditional branches and loops.

A non-zero delay model for glitch analysis in logic circuits

One of the major factors which contribute to the power consumption in CMOS combinational logic circuits is the switching activities in the circuits. Many of such switching activities are due to spurious pulses, called glitches. Recently, a new model of glitch analysis, called G-vector has been proposed. The power of the model is that, unlike the existing ones which model only the propagation of glitches to count the number of glitches in the circuits, it allows one to model the generation, propagation and elimination of glitches to be able to not only count the number of glitches but also locate the glitches. In this paper, we extend the concept of G-vector to support a non-zero delay model, which enables G-vector to be practically very efficient. A set of experimental results is provided to show the effectiveness of the proposed solution.

A complete model for glitch analysis in logic circuits

One of the major factors which contribute to the power consumption in CMOS combinational logic circuits is the switching activities in the circuits. Many such switching activities are due to spurious pulses, called glitches. Recently, a new model of glitch analysis, called G-vector has been proposed. The power of the model is that, unlike the existing ones which model only the propagation of glitches to count the number of glitches in the circuits, it allows one to model the generation, propagation and elimination of glitches to be able to not only count the number of glitches but also locate the glitches. In this paper, we complete the concept of G-vector by providing a set of efficient solutions to the two important practical issues: (1) extending to signals over multiple clock cycles, and (2) extending to a logic decomposition utilizing the model. Integrating the solutions all together enables G-vector to be very efficient. A set of experimental results is provided to show the effectiveness of the proposed solutions.