Taheni Damak

Fast prototyping H.264 Deblocking filter using ESL tools

This paper presents a design methodology for hardware/software (HW/SW) architecture design using ESL tools (Electronic System Level). From C++ descriptions, our design flow is able to generate hardware blocks running with a software part and all necessary codes to prototype the HW/SW system on Xilinx FPGAs. Therefore we use assistance of high level synthesis tools (Catapult C Synthesis), logic synthesis and Xilinx tools. As application, we developed an optimized Deblocking filter C code, designed to be used as a part of a complete H.264 video coding system [1]. Based on this code, we explored many configurations of Catapult Synthesis to analyze different area/time tradeoffs. Results show execution speedups of 95,5% compared to pure software execution etc.

DSP CAVLC implementation and optimization for H.264/AVC baseline encoder

Entropy coding is a fundamental stage in all video compression algorithms in terms of compression efficiency and error resilience. In this paper we propose and optimize a digital signal processor (DSP)-based implementation of the CAVLC tools for the H.264 Baseline encoder. As result, we have been able to generate the bit stream and supply bit rate result: the LETI encoder is able to achieve high compression performance when proposing interesting video quality.

An efficient zero length prefix algorithm for H.264 CAVLC decoder on TMS320C64

In this paper, an efficient DSP-based CAVLC decoding design is proposed. CAVLC decoding module takes the lion chair of our decoder execution time due to its complexity. In order to ameliorate CAVLC implementation, two major steps are proposed: First, we take advantage of DSP architecture by organizing its appropriate internal memory buffer to design a suitable CAVLC decoder architecture. Then, a zero length prefix algorithm (ZLP) is proposed to decode the first syntax element in CAVLC, called CoeffToken. This new algorithm permits amelioration in the CAVLC time execution by up to 20% which leads to an increase in the overall decoder speed by 8 fps. The decoder has been tested with different bitstreams. According to these tests, real time decoding can be obtained on a TMS320C6416 platform running at 720MHz.

Joint Selective Encryption of CAVLC and Signs of Motion Vectors for H.264/AVC

Currently, researchers are orienting their effort to selective encryption in order to protect video sequences against attacks during their transmission over a public channel. The reasons for this trend are of great importance. To reduce video data amount, the video compression chain is essential and to ensure their security, while in transmission, an encryption algorithm is evident. Thus, inserting the encryption module in the video compression chain is better than applying compression and encryption separately in terms of computing time. This paper presents a chaos based encryption method inserted in the H.264 Advanced Video Coding (AVC) used for video conferencing applications. The selective encryption was applied on context adaptive variable length coding (CAVLC) and on the signs of motion vectors. The results were deducted according to the values of peak signal to noise ratio (PSNR), structural similarity (SSIM) and the encryption rate (ER). Combining selective encryption of CAVLC (SE-CAVLC) and motion vector sign encryption (MVSE) are interesting in terms of enhancing the encryption and to damage the visual quality of the decoded video for both Intra and Inter predicted frames.

A very efficient encryption scheme for the H.264/AVC CODEC adopted in Intra prediction mode

The concept of data compression in CODECs is based on pixel prediction to avoid redundancy. For the security of data compressed with the H.264/AVC CODEC, researchers are thinking to selective encryption. This paper presents a chaos based encryption method inserted in the H.264/AVC used for video conferencing application. It consists of the encryption of Intra prediction mode. The results show that the proposed method preserves format compliance of the H.264/AVC and has a low impact on the compression ratio. It is secure and very efficient. Moreover it can be realized in real time application. The metrics used to evaluate our scheme are Peak Signal to Noise Ratio (PSNR), Structural SIMilarity (SSIM) and the Encryption Rate (ER). We also discuss the key sensitivity of our algorithm and histograms of encrypted videos.

DSP-based half-pel motion estimation implementation for H.264 baseline encoder

Motion Estimation module in H.264/AVC video encoder has the most computational load and memory access complexity, since it includes integer and fractional motion vector estimation. In the present paper, fractional motion estimation process analysis is performed based on which a Digital Signal Processor (DSP) specific optimized implementation is developed. The integration of the interpolation module decreases drastically the encoding speed when improving rate distortion performance. To overpass encoding speed degradation, parallelism between algorithm execution and data transfers were fully exploited using Enhanced Direct Memory Access engine (EDMA). Furthermore, based on the DSP architectural features, core specific optimization techniques were adopted leading to reduce the interpolation module complexity up to 70%.

HLS based design of a mixed architecture for H.264/AVC CAVLD

Mixed Hardware/Software architectures are often attractive solutions for Embedded System especially for real time applications. However, when the complexity of hardware functions grows, hand coding at Register-Transfer Level (RTL), which is already low and error prone, adds debugging and verification overheads that impact severely the time and costs of development. Therefore, High Level Synthesis (HLS) brings a solution to decrease the design time of dedicated hardware and keep the high abstraction level of software development. In this context we propose a HLS based design flow for Hardware/Software architecture on top of Catapult C Synthesis. We illustrate the effectiveness of this approach on the practical implementation example of a full H264/AVC video compression decoder. The hardware accelerator is the CAVLD module that takes 14% from the decoder execution time. Three architectures are presented for this module. The best one offers 85% of gain compared to software execution. The proposed architectures are implemented on a Xilinx FPGA-embedded systems prototyping board considering the PowerPC processor and a PLB bus for data communications with the CAVLC accelerator.

HLS and manual design methodology for H.264/AVC deblocking filter

This paper presents two design methodologies for hardware/software (HW/SW) architectures. The first one uses High Level Synthesis (HLS) based on Catapult C Synthesis. From C++ descriptions, this design flow is able to automatically produce hardware blocks that can fully operate with CPU cores on Xilinx prototyping platforms (FPGA). The second methodology relies on a manual RTL (Register Transfer Level) design to produce potentially better optimized IPs. To evaluate the performance of each flow, an application/design study using both methodologies is made on an optimized deblocking filter function, which is part of a complete H.264/AVC video coding system. A tradeoff between design time and performance is presented and discussed with respect to both methodologies: The HLS design flow time is less than the half of manual design flow time. However, the application throughput, in term of kilosMacroblock per second, is more than three times speeder when using a manual design.