Tahir A. Khan

Rugged Dotted-channel LDMOS structure

This paper presents the extremely robust and innovative dotted-channel structure which utilizes a unique approach of suppressing the parasitic bipolar to significantly improve the SOA and push the boundaries of LDMOS operation to a new realm. The structure has body contact placed through the poly-silicon gate of the standard MOSFET resulting in a hole (h+) collection site in front of the source which in turn shunts the base emitter path of the parasitic bipolar.

Combined Lateral Vertical RESURF (CLAVER) LDMOS structure

In this paper, a unique Combined Lateral Vertical RESURF (CLAVER) LDMOS structure is proposed for breakthrough performance. The structure uses a secondary RESURF design to terminate in the vertical direction to yield a much improved performance trade-off. The proposed device uses standard process steps available in integrated technology platforms to give a breakdown as high as 150V with ground-breaking on-state resistance of 159mOhm-mm2.

Bipolar Schottky rectifier: A novel two carrier Schottky rectifier based on superjunction concept

In this paper, a novel Schottky diode structure based on the superjunction concept is proposed. The concept is based on 2-carrier current conduction and utilizes both P and N columns for current conduction. The proposed device utilized the P and N superjunction columns to achieve high breakdown with low leakage current.

Incremental FRESURF LDMOSFET structure for enhanced voltage blocking capability on a 0.13μm, SOI based technology

In this paper, a novel structure based on the Floating RESURF LDMOSFET is proposed for enhanced off-state blocking capability. The new structure facilitates the implementation of FRESURF concept in thicker epi technologies for higher voltage tiers. An additional floating island is introduced, sandwiched between the standard drift region and heavily doped buried layer, which makes the Incremental FRESURF action feasible. Best case BVDSS of 130V with RDS,ON of 1.6mω-cm2 has been experimentally realized on a 0.13μm, SOI based smart power technology which is a significant improvement as compared to other state of the art integrated high voltage technologies

5.5 V zero-channel power MOSFETs with R on,sp of 1.0 mΩ·mm 2 for portable power management applications

We report on the experimental demonstration of revolutionary 5.5 V zero-channel power MOSFETs with record low specific on-resistance of 1.0 m#x2126;·mm² and Figure of Merit (R<inf>on</inf>×Q<inf>g</inf>) of 8.4 m#x2126;·nC with optimized metal layout. This novel device also shows good Hot Carrier Injection (HCI) immunity.

Impact of Deep Sub-Micron Design Rules on Optimization of RESURF LDMOSFETs

In this paper we demonstrate and evaluate the impact of deep sub-micron design rules on the performance of RESURF LDMOSFET devices in smart power technologies. It is observed that the device parameters such as breakdown voltage, specific on-resistance, safe operating area (SOA) depend significantly on the width of the drain active opening. Simply reducing the active opening width to minimum allowed by the technology design rules may not always yield best device performance. In deep sub-micron smart power technologies where one or two implants are often utilized to construct variety of devices for multiple voltage-tiers, this can provide an effective tool for device performance