Vishnu K. Khemka

SOA improvement by a double RESURF LDMOS technique in a power IC technology

This paper presents a technique that provides double RESURF action in a lateral power MOSFET controlled through an independently biased terminal thereby realizing a two-fold improvement in electrical static SOA over single RESURF lateral device structures at high drain voltages. The technique has been successfully implemented to realize a high-side capable lateral power MOSFET with BV/sub dss/ of 61 V and specific on-resistance (R/sub dson/A) of 0.54 m/spl Omega/-cm/sup 2/ and with a maximum electrical static operating current of 1.9 A/cm at a drain to source voltage of 54 V.

Implementation of high-side, high-voltage RESURF LDMOS in a sub-half micron smart power technology

55 V high-side RESURF LDMOS has been integrated successfully in 0.35 /spl mu/m smart power technology by carefully arranging the lateral doping profile. This device has Rds.on/spl times/area of 0.55 m/spl Omega/.cm/sup 2/ with excellent safe operating area. With proper device terminal biasing scheme, this device can also be used as an isolated device. Techniques and issues related to the isolation is considered and discussed.

Stepped-Drift LDMOSFET: A Novel Drift Region Engineered Device for Advanced Smart Power Technologies

A novel drift region engineered stepped-drift LDMOSFET device in Freescales 0.25mum smart power technology is reported for the first time. The specific on-resistance of the device is 0.33 mOmegamiddotcm2 at breakdown voltage of 59 V, the best reported data to date. SOA of the device has been improved up to 87% compared to its conventional counterpart

Novel FRESURF LDMOSFET devices with improved BV/sub dss/-R/sub dson/

In this letter, we propose and demonstrate a novel device based on a floating reduced surface field (FRESURF) concept which allows the realization of significantly higher breakdown voltage in a thin epitaxy-based power IC technology. The newly proposed device with the floating buried layer pulled back from the source side is able to realize an enhanced breakdown voltage (BV/sub dss/) without degrading the specific on-resistance (R/sub dson/A). BV/sub dss/-R/sub dson/A values like 47 V-0.28 m/spl Omega//spl middot/cm/sup 2/ or 93 V-0.82 m/spl Omega//spl middot/cm/sup 2/ have been realized with a conventional power IC technology without any added process complexity.

Rugged Dotted-channel LDMOS structure

This paper presents the extremely robust and innovative dotted-channel structure which utilizes a unique approach of suppressing the parasitic bipolar to significantly improve the SOA and push the boundaries of LDMOS operation to a new realm. The structure has body contact placed through the poly-silicon gate of the standard MOSFET resulting in a hole (h+) collection site in front of the source which in turn shunts the base emitter path of the parasitic bipolar.

Substrate Majority Carrier-Induced NLDMOSFET Failure and Its Prevention in Advanced Smart Power IC Technologies

This paper discusses substrate majority carrier conduction and prevention for an n-type lateral double diffused MOSFET (NLDMOSFET) device in Smart Power IC technologies. Substrate majority carrier current poses severe electrical and thermal stress for NLDMOSFET devices and causes many system integration issues for advanced Smart Power IC technologies. A single- and multi-iso isolated NLDMOSFET is proposed and experimentally verified to eliminate the problem. Tradeoff between device size, safe operating area (SOA), substrate current, and NLDMOSFET-device power dissipation has been studied. Detailed analysis of device SOA for conventional and isolated devices and techniques to improve the device SOA has also been provided

A 0.35 /spl mu/m CMOS based smart power technology for 7 V-50 V applications

This paper describes a 0.35 /spl mu/m smart power technology that enables integration of a diverse set of analog and high-voltage power components in a 0.35 /spl mu/m CMOS logic platform for a broad range of voltage applications from 7 V to 50 V.

HMS rectifier: a novel hybrid MOS Schottky diode concept with no barrier lowering, low leakage current and high breakdown voltage

In this paper we propose and demonstrate a novel Schottky device concept, which is capable of achieving ultra low leakage current with high breakdown voltage. The proposed Schottky diode is conceived and designed with a lateral configuration for deep sub-micron smart power technologies but can also be designed in a vertical discrete configuration. A combination of depletion mode MOSFET and n or p-type Schottky junctions are utilized to create hybrid MOS Schottky (HMS) diode where the high reverse bias voltage is blocked by the MOSFET. The device is first demonstrated in a circuit configuration with discrete Schottky diode and a MOSFET. Subsequently, low separate monolithic integrated versions of the diode are proposed and realized. The integrated version of the diode achieved near-ideal characteristics with an ideality factor, n of 1.04 and a barrier height o/sub B/ of 0.64eV.

Combined Lateral Vertical RESURF (CLAVER) LDMOS structure

In this paper, a unique Combined Lateral Vertical RESURF (CLAVER) LDMOS structure is proposed for breakthrough performance. The structure uses a secondary RESURF design to terminate in the vertical direction to yield a much improved performance trade-off. The proposed device uses standard process steps available in integrated technology platforms to give a breakdown as high as 150V with ground-breaking on-state resistance of 159mOhm-mm2.

A 65 V, 0.56 m/spl Omega/.cm/sup 2/ Resurf LDMOS in a 0.35 /spl mu/m CMOS process

This paper reports a 65 V, 0.56 m/spl Omega/.cm/sup 2/ Resurf LDMOS with a wide safe operating area integrated into a 0.35 /spl mu/m CMOS process. The superior performance of the device is achieved by advanced implantation techniques without additional thermal steps and without resorting to high-tilt implants.