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Featured researches published by Tai-Ji An.


IEEE Transactions on Very Large Scale Integration Systems | 2013

Time-Interleaved and Circuit-Shared Dual-Channel 10 b 200 MS/s 0.18

Hyo-Jin Kim; Tai-Ji An; Sung-Meen Myung; Seung-Hoon Lee

This paper proposes a 10 b 200 MS/s pipeline analog-to-digital convertor (ADC) for high-quality video systems based on double-channel and op-amp sharing schemes to minimize power consumption and channel mismatch. The double channel time-interleaved scheme reduces the required operating speed of amplifiers in the sample-and-hold amplifier and multiplying digital-to-analog (D/A) converters by 50%. The switched and shared op-amp with two input pairs amplifies each channel signal without extra series switches while minimizing the gain, bandwidth and offset mismatches between channels. The low-jitter sampling clock with a 50% duty cycle improves the dynamic performance of the wideband input signals significantly. The Flash ADCs employ a differential difference amplifier type pre-amp to continuously process dual-channel outputs. The prototype ADC in a 0.18 μm CMOS technology demonstrates the measured differential nonlinearity and integral nonlinearity within 0.62 and 0.99 LSB, respectively. At 200 MS/s, the ADC shows a maximum SNDR of 52.8 dB and a maximum SFDR of 60.4 dB. The ADC with an active die area of 1.28 mm2 consumes 54.0 mW at 1.8 V.


Journal of Semiconductor Technology and Science | 2013

\mu{\rm m}

Dong-Hyun Hwang; Jung-Eun Song; Sang-Pil Nam; Hyojin Kim; Tai-Ji An; Kwang-Soo Kim; Seunghoon Lee

This work describes a 13b 100 MS/s 0.13um CMOS four-stage pipeline ADC for 3G communication systems. The proposed SHA-free ADC employs a range-scaling technique based on switched-capacitor circuits to properly handle a wide input range of 2VP-P using a single on-chip reference of 1VP-P. The proposed range scaling makes the reference buffers keep a sufficient voltage headroom and doubles the offset tolerance of a latched comparator in the flash ADC1 with a doubled input range. A two-step reference selection technique in the back-end 5b flash ADC reduces both power dissipation and chip area by 50%. The prototype ADC in a 0.13 um CMOS demonstrates the measured differential and integral nonlinearities within 0.57 LSB and 0.99 LSB, respectively. The ADC shows a maximum signal-to-noise-and-distortion ratio of 64.6 dB and a maximum spurious-free dynamic range of 74.0 dB at 100 MS/s, respectively. The ADC with an active die area of 1.2 mm2 consumes 145.6 mW including high-speed reference buffers and 91 mW excluding buffers at 100 MS/s and a 1.3 V supply voltage.


Journal of Semiconductor Technology and Science | 2014

CMOS Analog-to-Digital Convertor

Jun-Sang Park; Tai-Ji An; Suk-Hee Cho; Yongmin Kim; Gil-Cho Ahn; Ji-Hyun Roh; Mun-Kyo Lee; Sun-Phil Nah; Seunghoon Lee

This work proposes a 12b 100 MS/s 0.11 m CMOS three-step hybrid pipeline ADC for high- speed communication and mobile display systems requiring high resolution, low power, and small size. The first stage based on time-interleaved dual- channel SAR ADCs properly handles the Nyquist-rate input without a dedicated SHA. An input sampling clock for each SAR ADC is synchronized to a reference clock to minimize a sampling-time mismatch between the channels. Only one residue amplifier is employed and shared in the proposed ADC for the first-stage SAR ADCs as well as the MDAC of back-end pipeline stages. The shared amplifier, in particular, reduces performance degradation caused by offset and gain mismatches between two channels of the SAR ADCs. Two separate reference voltages relieve a reference disturbance due to the different operating frequencies of the front-end SAR ADCs and the back-end pipeline stages. The prototype ADC in a 0.11 m CMOS shows the measured DNL and INL within 0.38 LSB and 1.21 LSB, respectively. The ADC occupies an active die area of 1.34 mm 2 and consumes 25.3 mW with a maximum SNDR and SFDR of 60.2 dB and 69.5 dB, respectively, at 1.1 V and 100 MS/s.


international soc design conference | 2012

A Range-Scaled 13b 100 MS/s 0.13 um CMOS SHA-Free ADC Based on a Single Reference

Sang-Pil Nam; Yong-Min Kim; Dong-Hyun Hwang; Hyo-Jin Kim; Tai-Ji An; Jun-Sang Park; Suk-Hee Cho; Gil-Cho Ahn; Seung-Hoon Lee

This work proposes a 10b 1MS/s-to-10MS/s 0.11um CMOS SAR ADC optimizing power consumption and chip area for analog TV (NTSC/PAL) applications. The proposed DAC employs a 2-step (6b-4b) split-capacitor array with the VCM-based switching method for high power efficiency and small chip area. Additionally, a range-scaling technique is employed for a rail-to-rail input signal swing. The comparator accuracy is improved by offset cancellation techniques in the first-stage pre-amp. The prototype ADC in a 0.11um CMOS technology demonstrates the measured DNL and INL within 1.07LSB and 1.66LSB, respectively. The ADC shows a maximum SNDR of 54.4dB and a maximum SFDR of 69.8dB at 10MS/s, respectively. The ADC with an active die area of 0.25mm2 consumes 2.3mW at a 1.2V and 10MS/s.


Journal of Semiconductor Technology and Science | 2016

A 12b 100 MS/s Three-Step Hybrid Pipeline ADC Based on Time-Interleaved SAR ADCs

Jun-Sang Park; Jong-Min Jeong; Tai-Ji An; Gil-Cho Ahn; Seunghoon Lee

This paper proposes a low-power rangescaled 14b 30 MS/s pipeline-SAR composite ADC for high-performance CIS applications. The SAR ADC is employed in the first stage to alleviate a samplingtime mismatch as observed in the conventional SHA-free architecture. A range-scaling technique processes a wide input range of 3.0VP-P without thick-gate-oxide transistors under a 1.8 V supply voltage. The firstand second-stage MDACs share a single amplifier to reduce power consumption and chip area. Moreover, two separate reference voltage drivers for the firststage SAR ADC and the remaining pipeline stages reduce a reference voltage disturbance caused by the high-speed switching noise from the SAR ADC. The measured DNL and INL of the prototype ADC in a 0.18 μm CMOS are within 0.88 LSB and 3.28 LSB, respectively. The ADC shows a maximum SNDR of 65.4 dB and SFDR of 78.9 dB at 30 MS/s, respectively. The ADC with an active die area of 1.43 mm 2 consumes 20.5 mW at a 1.8 V supply voltage and 30 MS/s, which corresponds to a figure-of-merit (FOM) of 0.45 pJ/conversion-step.


international soc design conference | 2015

A 10b 1MS/s-to-10MS/s 0.11um CMOS SAR ADC for analog TV applications

Jong-Min Jeong; Tai-Ji An; Hee-Wook Shin; Gi-Wook Lee; Seung-Hoon Lee

This work proposes a 12b 30MS/s 0.18μm SAR ADC based on a low-power composite switching technique to reduce the required number of capacitors and switching energy. The proposed composite switching employs VCM-based switching and monotonic switching sequences while minimizing the switching power consumption of a DAC and the dynamic offset to constrain a linearity of the SAR ADC. A split capacitor topology implements the VCM-based switching scheme effectively without extra switches in the DAC and the SAR logic. Moreover, the proposed C-R hybrid DAC architecture minimizes the DAC area by reducing the total number of unit capacitors in the DAC up to 32. The prototype ADC in a 0.18μm CMOS technology occupies an active die area of 0.16mm2 and consumes 1.93mW at a 1.8 V supply voltage without on-chip I/V references.


international symposium on circuits and systems | 2013

Range-Scaled 14b 30 MS/s Pipeline-SAR Composite ADC for High-Performance CMOS Image Sensors

Tai-Ji An; Jun-Sang Park; Yong-Min Kim; Suk-Hee Cho; Gil-Cho Ahn; Seung-Hoon Lee

A 10b 150MS/s 0.4mm2 pipeline ADC is implemented in a 45nm CMOS process. The input SHA, employing four charge-redistributed capacitors, converts single-ended or differential input signals of 1.2Vpp to differential outputs of 0.8Vpp for a low supply voltage of 1.1V. The process-insensitive high-gain amplifiers in the SHA and MDACs are based on gain-boosting, pseudo-differential output pair, and continuous-time common-mode feedback circuits to overcome various performance limitations that are observed in deep nanometer CMOS technologies. The MDAC2 and MDAC3 share a single high-gain amplifier to reduce the input memory effect, chip area, and power dissipation. The measured DNL and INL are within 1.06 and 1.29LSB, respectively. At 150MS/s, the prototype ADC shows a maximum SNDR of 51.8dB and a maximum SFDR of 63.7dB with a 1.2Vpp sinusoidal input and consumes 47.3mW.


international soc design conference | 2013

A 0.16mm2 12b 30MS/s 0.18μm CMOS SAR ADC based on low-power composite switching

Jun-Sang Park; Tai-Ji An; Yong-Min Kim; Suk-Hee Cho; Hyun-Sun Shim; Woo-Jin Jang; Yong-Jin Shin; Jun-Hyup Lee; Gil-Cho Ahn; Seung-Hoon Lee

This work proposes a skinny-shape 10b 50MS/s 90nm CMOS four-step pipeline ADC for various CIS applications. The proposed ADC converts analog signals in variable signal-swing ranges of 1.12 to 1.60Vp-p into low voltage-based digital data. The proposed on-chip I/V reference circuits generate the required variable reference voltages with a fixed common-mode level using a single external control voltage. The prototype ADC implemented in a 90nm CMOS process shows a maximum SNDR and SFDR of 55.1dB and 65.6dB, respectively. The ADC with an active die area of 0.23mm2 consumes 17.5mW at 50MS/s using dual supply voltages of 2.5V for analog and 1.2V for digital.


international soc design conference | 2011

10b 150MS/s 0.4mm 2 45nm CMOS ADC based on process-insensitive amplifiers

Dong-Hyun Hwang; Jung-Eun Song; Sang-Pil Nam; Hyo-Jin Kim; Tai-Ji An; Kwangsoo Kim; Seung-Hoon Lee

This work describes a 13b 100MS/s 0.13μm CMOS four-step pipeline ADC. The proposed SHA-free ADC employs a range-scaling technique based on switched-capacitor circuits properly to handle input signals twice as wide as a single on-chip reference range in the first pipeline stage. The range scaling makes reference driving buffers keep a sufficient dynamic voltage headroom and doubles the offset tolerance of a latched comparator without a pre-amp in the flash ADC1. The prototype ADC demonstrates the measured DNL and INL within 0.57LSB and 0.99LSB, respectively. The ADC shows a maximum SNDR of 64.6dB and a SFDR of 74.0dB at 100MS/s, respectively. The ADC with an active die area of 1.2mm2 consumes 145.6mW including the high-speed reference buffers and 91mW excluding the buffers at 100MS/s and a 1.3V supply voltage.


Iet Power Electronics | 2016

A 10b 50MS/s 90nm CMOS Skinny-Shape ADC Using Variable References for CIS Applications

Tai-Ji An; Gil-Cho Ahn; Seung-Hoon Lee

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