Gil-Cho Ahn

A 0.6-V 82-dB delta-sigma audio ADC using switched-RC integrators

A 0.6-V 2-2 cascaded audio delta-sigma ADC is described. It uses a resistor-based sampling technique which achieves high linearity and low-voltage operation without subjecting the devices to large terminal voltages. A low-distortion feed-forward topology combined with nonlinear local feedback results in enhanced linearity by reducing the sensitivity to opamp distortion, and allows increased input amplitude, resulting in higher SNDR. The modulator achieves 82-dB dynamic range and 81-dB peak SNDR in the A-weighted audio signal bandwidth with an OSR of 64. The total power consumption of the modulator is 1 mW from a 0.6-V supply. The prototype occupies 2.9 mm/sup 2/ using a 0.35-/spl mu/m CMOS technology.

A 0.9 V 92 dB Double-Sampled Switched-RC Delta-Sigma Audio ADC

A 0.9 V third-order double-sampled delta-sigma audio ADC is presented. A new method using a combination of a switched-RC technique and a floating switched-capacitor double-sampling configuration enabled low-voltage operation without clock boosting or bootstrapping. A three-level quantizer with simple dynamic element matching was used to improve linearity. The prototype IC implemented in a 0.13 CMOS process achieves 92 dB DR, 91 dB SNR and 89 dB SNDR in a 24 kHz audio signal bandwidth, while consuming 1.5 mW from a 0.9 V supply. The prototype operates from 0.65 V to 1.5 V supply with minimal performance degradation.

Sub-1-V design techniques for high-linearity multistage/pipelined analog-to-digital converters

The design of an ultra-low-voltage multistage (two-stage algorithmic) analog-to-digital converter (ADC) employing the opamp-reset switching technique is described. A highly linear input sampling circuit accommodates truly low-voltage sampling from external input signal source. A radix-based digital calibration technique is used to compensate for component mismatches and reduced opamp gain under low supply voltage. The radix-based scheme is based on a half-reference multiplying digital-to-analog converter structure, where the error sources seen by both the reference and input signal paths are made identical for a given stage. The prototype ADC was fabricated in a 0.18-/spl mu/m CMOS process. The prototype integrated circuit dissipates 9 mW at 0.9-V supply with an input signal range of 0.9 V/sub p-p/ differential. The calibration of the ADC improves the signal-to-noise-plus-distortion ratio from 40 to 55 dB and the spurious-free dynamic range from 47 to 75 dB.

A 12 bit 50 MS/s CMOS Nyquist A/D Converter With a Fully Differential Class-AB Switched Op-Amp

A 12 bit 50 MS/s 1.8 V pipelined CMOS analog-to-digital converter (ADC) based on a fully differential class-AB switched operational amplifier achieves low power consumption with a differential input voltage of 2.4 Vp-p. A global-loop dynamic common-mode feedback circuit enables fully differential class-AB operation with dynamic current switching for power reduction. The prototype ADC shows a peak signal-to-noise-and-distortion ratio of 64.0 dB and a peak spurious-free dynamic range of 76.6 dB for a 31 MHz input signal at 50 MS/s while the measured differential and integral nonlinearities are within ±0.26 LSB and ±0.72 LSB, respectively. The prototype ADC in a 0.18 ¿m 1P6M CMOS process consumes 18.4 mW at 50 MS/s and 1.8 V occupying an active die area of 0.26 mm2.

A 12 b 10 MHz 250 mW CMOS A/D converter

In high-speed and high-resolution ADCs, self-calibration techniques have widely been used to improve linearities by subtracting ADC nonlinear errors in digital domain. However, stand-alone self-calibrated ADC systems employing a CMOS process have not been fully integrated on a single chip. This fully-differential 12 b 4-stage pipelined CMOS ADC uses a modified digital-domain nonlinear error calibration technique. All functional blocks including digital calibration logic, 16 B memory, and bias circuits are fully integrated on a single chip. The ADC is optimized to improve linearity and yield and uses a mid-rise coding technique that is more efficient in using identical circuit blocks repeatedly than a conventional mid-tread coding. As a result, a modular circuit design approach is applied to the proposed ADC, easily modified for 10 b or 14 b resolution by eliminating or adding an identical stage.

A 1.2-V 12-b 120-MS/s SHA-Free Dual-Channel Nyquist ADC Based on Midcode Calibration

This paper describes a 12-b 120-MS/s dual-channel pipeline analog-to-digital converter (ADC) for high-speed video signal processing. A simple digital midcode calibration technique is proposed to eliminate an offset mismatch between two channels. The proposed sample-and-hold-amplifier-free architecture with correlated input sampling networks enables wideband signal sampling while effectively reducing a gain mismatch between channels. The prototype ADC implemented in a 0.13-¿m CMOS technology achieves a peak signal-to-noise-and-distortion ratio of 61.1 dB and a peak spurious-free dynamic range of 74.7 dB for input frequencies up to 60 MHz at 120 MS/s. The measured differential and integral nonlinearities are within ±0.30 LSB and ±0.95 LSB, respectively. The ADC occupies an active die area of 0.56 mm2 and consumes 51.6 mW at a 1.2 V power supply.

A 9.43-ENOB 160MS/s 1.2V 65nm CMOS ADC based on multi-stage amplifiers

A 12-bit 1.2V 160MS/s pipeline ADC for high-definition video systems is presented. The proposed multipath frequency-compensation technique enables the conventional RNMC-based three-stage amplifier to achieve a stable operation at a sampling rate of 160MS/s. The measured differential and integral nonlinearities of the prototype ADC implemented in a 65nm CMOS process are less than 0.69LSB and 1.00LSB respectively. The ADC shows a maximum SNDR of 58.5dB and 53.1dB and a maximum SFDR of 76.0dB and 67.8dB at 160MS/s and 200MS/s, respectively. The ADC with an active die area of 0.72mm2 shows a FoM of 0.75pJ/conv-step at 160MS/s and 1.2V.

A ΔΣ ADC using 4-bit SAR type quantizer for audio applications

This paper presents a second-order delta-sigma modulator for audio applications. It uses feed-forward architecture and 4-bit quantizer to enhance linearity and noise performance. A 4-bit successive approximation (SAR) analog-to-digital converter (ADC) with summing operation is implemented to reduce power consumption by eliminating the active summing amplifier. In order to reduce the distortion resulted from the capacitor mismatch of the feedback digital-to-analog converter (DAC), a tree-structured dynamic element matching (DEM) is employed. The prototype delta-sigma ADC implemented in a 45 nm CMOS process occupies 231.2 μm2 and achieves a dynamic range (DR) of 94.0 dB, a peak signal-to-noise ratio (SNR) of 92.1 dB and a peak signal-to-noise and distortion ratio (SNDR) of 84.5 dB for 24 kHz signal bandwidth, while consuming 8.2 mW with 3.3 V supply.

A 10-bit 100-MS/s Dual-Channel Pipelined ADC Using Dynamic Memory Effect Cancellation Technique

This brief presents a 10-bit 100-MS/s 1.2-V dual-channel pipelined CMOS analog-to-digital converter (ADC). The nine dual-channel pipelined stages share the operational amplifiers (op-amps) to optimize power and area. The proposed dynamic memory effect cancellation technique reduces the cross coupling caused by the residual charge in the op-amp sharing topology. The op-amp gain requirement of the dual-channel sample-and-hold circuit is also relaxed by the proposed memory effect cancellation technique. The prototype ADC achieves a peak signal-to-noise and distortion ratio of 56 dB for a 1-MHz input signal and a peak cross-coupling ratio of 67.4 dB at 100 MS/s while consuming 16.2 mW/channel from a 1.2-V supply. The prototype ADC occupies 1.96 mm2 using a 0.13-μm CMOS technology.

A 0.9V 92dB Double-Sampled Switched-RC SD Audio ADC

A 0.9V third-order 1.5bit delta-sigma ADC with simple dynamic element matching (DEM) is presented. A fully-differential low-voltage double-sampling structure avoids use of clock boosting or bootstrapping. It operates from 0.65V to 1.5V supply with minimal performance degradation. The prototype IC implemented in a 0.13mum CMOS process achieves 92dB DR, 91dB SNR and 89dB SNDR, while consuming 1.5mW from a 0.9V supply