Tai-song Jin

JTS-based static branch prediction

VLIW architectures are popular design choices in embedded computing market because of its capability of delivering performance with low power. Branch prediction plays a key role for minimizing pipeline stalls due to control hazard. Though a hardware branch predictor can result in good predictions, its HW cost often hinders it from being used in low-power VLIW architectures. On the other hand, a software branch prediction by the compiler can achieve comparable prediction quality utilizing delay slots intelligently without HW cost. In this paper, we propose a novel static branch prediction technique using jump target setting (JTS) instructions. The JTS-enabled VLIW architecture is successfully shipped in several commercial consumer electronic devices from Samsung. In our experiment using multimedia applications, the proposed branch prediction scheme outperforms the conventional static branch prediction with delay slots by 9%.

Nop compression scheme for high speed DSPs based on VLIW architecture

VLIW (Very Long Instruction Word) is one of the most popular architectures in embedded systems because it has features of low power consumption and low hardware cost. Due to the nature of VLIW architecture such as bundled instructions and large register files, VLIW processors are running with large size of instruction codes in relatively low clock frequency. However compact instruction size and high clock frequency are the most important requirements of modern embedded consumer electronics. In this paper we propose a novel instruction compression scheme to solve the addressed problem. The experiment shows that the proposed scheme can reduce instruction size by 23% and improve clock frequency by 25% in average comparing with conventional compression schemes.