Taimur Gibran Rabuske

An 8-bit 0.35-V 5.04-fJ/Conversion-Step SAR ADC With Background Self-Calibration of Comparator Offset

This paper reports a successive approximation register (SAR) analog-to-digital converter (ADC) based on the charge-sharing principle, which is known to be very energy efficient, but susceptible to the comparator offset. The ADC uses a new background calibration technique to cancel out the comparator mismatch and improve ADC linearity. Operation under low voltages is obtained through the use of voltage-boosted switches in the track-and-hold and the digitalto-analog converter. The techniques are demonstrated on a low-voltage low-power SAR ADC that operates from a minimum supply voltage of 350 up to 600 mV, suitable for circuits supplied by power harvesters. The prototype fabricated in a 130-nm CMOS process employs only regular-VTH transistors. It is able to convert at 3 MSps when supplied by 600 mV and at 200 kSps when supplied by 350 mV. At 350 mV, the measured effective-number-of-bits is 6.4, leading to a figure-of-merit of 5.04 fJ/conversion-step.

Quaternary Logic Lookup Table in Standard CMOS

Interconnections are increasingly the dominant contributor to delay, area and energy consumption in CMOS digital circuits. Multiple-valued logic can decrease the average power required for level transitions and reduces the number of required interconnections, hence also reducing the impact of interconnections on overall energy consumption. In this paper, we propose a quaternary lookup table (LUT) structure, designed to replace or complement binary LUTs in field programmable gate arrays. The circuit is compatible with standard CMOS processes, with a single voltage supply and employing only simple voltagemode structures. A clock boosting technique is used to optimize the switches resistance and power consumption. The proposed implementation overcomes several limitations found in previous quaternary implementations published so far, such as the need for special features in the CMOS process or power-hungry current-mode cells. We present a full adder prototype based on the designed LUT, fabricated in a standard 130-nm CMOS technology, able to work at 100 MHz while consuming 122 μW. The experimental results demonstrate the correct quaternary operation and confirm the power efficiency of the proposed design.

A 9-b 0.4-V charge-mode SAR ADC with 1.6-V input swing and a MOSCAP-only DAC

The linearity of the vast majority of the ADC topologies is limited by the linearity of the employed circuit elements, e.g. resistors and capacitors. This paper presents a 9-b charge-mode SAR ADC that uses only very nonlinear MOSCAPs as the DAC capacitance elements and still presents 67 dB of SFDR. The track-and-hold exploits the routing parasitics as the sampling capacitance, entirely obviating MOM capacitors in the design. The circuit employs local voltage boosting and a new boost-and-bootstrap switch in order to allow operation under 0.4 V of supply voltage. Still, the ADC topology achieves a differential input swing of 1.6 Vpp, which is four times the supply voltage. The 0.13-μm CMOS prototype achieves an ENOB of 8.01 at 300 kSps while consuming 354 nW. The corresponding FoM is 4.57 fJ/conversion-step.

A 5-bit 300–900-MS/s 0.8–1.2-V Supply Voltage ADC With Background Self-Calibration

Low-power, high-speed, and low-resolution analog-to-digital converters (ADCs) are mandatory for a wide range of modern applications. In this brief, a background-calibrated low-power 5-bit comparator-based binary-search ADC is presented. The ADC, which was implemented in a 130-nm complementary metal-oxide-semiconductor process, can compensate for process-voltage-temperature variations on-the-fly and offers state-of-the-art figure of merit (FoM) for the set of specifications. Multiple track-and-hold working in time interleaving are employed to enable increased conversion speed at low power consumption, whereas the comparator stages operate in amplifierless pipelining. As the comparators present a significant offset spread due to process variations, the thresholds are concurrently calibrated with the conversion using a reference digital-to-analog converter. The ADC operates with supply voltages ranging from 0.8 to 1.2 V. When supplied with 0.8 V, the ADC performs up to 300 MS/s and presents 28.13 dB, 235 μW, and 39.4 fJ/conversion step of signal-to-noise-and-distortion ratio (SNDR), power consumption, and FoM, respectively. With 1.2 V of supply, the ADC performs up to 900 MS/s and presents 27.83 dB of SNDR, 1.54 mW of power consumption, and 82.5 fJ/conversion step of FoM.

A SAR ADC With a MOSCAP-DAC

The linearity of the vast majority of the ADC topologies is limited by the linearity of the circuit elements employed in their design, such as resistors and capacitors. This paper presents a charge-mode SAR ADC architecture that uses only highly nonlinear metal-oxide-semiconductor capacitors (MOSCAPs) as the DAC capacitance elements. The non-linearity of the MOSCAPs is exploited to improve the tolerance of the ADC to comparator offset and noise. The architecture employs local voltage boosting and a new boost-and-bootstrap switch to allow operation with an over-rails input range. A 9 bit prototype is fabricated in a 0.13 μm CMOS process and operates with a supply voltage of 0.6 V, handling a differential input range of 1.7 Vpp. The prototype achieves an effective number of bits (ENOB) larger than 8.5 for a temperature range of -40 to 85°C, despite the strong dependency of MOSCAPs to temperature. Operating at 1 MSps, the prototype consumes 2.78 μW, leading to a figure of merit (FoM) of 7.8 fJ/conversion-step.

Fast settling VGA for eddy currents non-destructive testing with an array of magneto resistors

This paper presents a low noise CMOS circuit for precise reading of an array of magnetoresistive sensors. The settling time of the low frequency AC coupled amplifier defines the reading speed for the sensors, being usually very long due to the large time constants. We present a fast settling mechanism that momentarily reduces the resistance defining the high-pass filter pole and changes it back to the initial value when the signal crosses zero, to avoid glitches. A logic circuit for zero cross detection based on a reference signal is implemented together with a delay matching circuit. This technique has been validated by measurements in a simplified discrete prototype and by simulation in an ASIC implemented in AMS 0.35 μm technology. The ASIC has a simulated 30 nV/√Hz noise at 1 kHz, a bandwidth from 100 Hz to 10 MHz, and a settling time of T/2, being T the period of the signal.

Analysis and Background Self-Calibration of Comparator Offset in Loop-Unrolled SAR ADCs

In conventional charge redistribution successive approximation register (SAR) ADCs that use a single comparator, the comparator offset causes no distortion but a dc shift in the transfer curve. In loop-unrolled (LU) SAR ADCs, on the other hand, mismatched comparator offset voltages introduce input-level-dependent errors to the conversion result, which deteriorates the linearity and limits the resolution. Still, the literature lacks a quantitative analysis on this phenomenon, and the resolution of most reported SAR ADCs of this kind, until recently, has been limited to 6 bit. In this paper, we analyze the effects of comparator offset voltage mismatch in LU-SAR ADCs, and establish the quantitative relation between individual offsets and the signal-to-noise-and-distortion ratio (SNDR) and the effective-number-of-bits. A statistical linearity model is proposed for yield estimation. Finally, an on-line deterministic calibration technique for auto-zeroing dynamic comparator offset is presented to treat the offsets mismatch and improve linearity. A 150-MS/s 8-bit LU-SAR ADC is fabricated in a 130-nm CMOS technology to validate the concept. The measured result shows that the calibration improves the SNDR from 33.7 to 42.9 dB. The ADC consumes

Tunable kΩ to GΩ pseudo-resistor with bootstrapping technique

640~\mu \text{W}

A 12-bit SAR ADC with background self-calibration based on a MOSCAP-DAC with dynamic body-biasing

from a 1.2-V supply with a figure-of-merit of 37.5 fJ/conv-step.

A sub-ranging 2-Step 7-bit self-calibrated comparator-based binary-search ADC

This paper presents a novel architecture for a kilo-ohm to giga-ohm pseudo-resistor (PR), based on transistors operating in subthreshold with a fixed-Vgs configuration. This PR when used in an RC filter has a very low and constant settling time regardless of the programmed pole frequency. The proposed PR takes advantage of bootstrapping to improve its tuning range. By defining a constant VGs for the transistors using a pre-charged capacitor, voltages from GND to VDD can be used and the transistor can be tuned to work from the cut-off region (for high resistances in the order of giga-ohms) to the deep triode region (for low resistances in the order of kilo-ohms). The disclosed PR can be used in the DC feedback loop of a capacitively coupled amplifier, enabling a bandwidth tuning range of 9 decades (mHz to MHz). Moreover, by using the pre-charge period to connect the gate of the PR transistor to ground, the amplifier settles in less than 1 μs, conforming with applications where electrodes/sensors with different nominal impedances are multiplexed to the amplifier input. The amplifier and the PR were validated in a 0.35 μm CMOS process, with post-layout simulations.