Taira Iwase

A 16 Mb mask ROM with programmable redundancy

In response to demands for a mask ROM with large bit capacity, a 1M-word*16 bit mask ROM with 120-ns access time has been fabricated. A programmable redundancy technique utilizes electrically fusible polysilicon links with the secondary breakdown mechanism of a MOSFET for high production yield and small chip area. The memory cell matrix arranged in 8192 rows*2048 columns and is divided into four blocks by two sets of row decoders in order to reduce word line delay. The redundancy cell array is composed of 8 rows*256 columns which can replace four defective quarter-rows. The mask ROM is fabricated in single-polysilicon single-aluminium twin-well CMOS technology with 0.7- mu m photolithography for high bit density. The process parameters and design features of the mask ROM are given together with a block diagram.<<ETX>>

A 70ns 2Mb mask ROM with a programmed memory cell

This report will cover the development of a 70ns 2Mb CMOS mask ROM with a through-hole programmed memory, using double-poly layers and self-aligned contact. With 1.5μm design rules, the die measures 6.57 × 11.9mm.