Taishi Kimura

Self‐temperature‐control plane heaters by graphite‐polyethylene glycol mixed systems

Mixed systems of graphite carbon and polyethylene glycol are found to show an anomalous increase in electrical resistance at certain temperatures. Making use of this property, we have made plane heaters of these graphite carbon‐polyethylene glycol mixed systems. These heaters, when the power was supplied, maintained constant temperature without any temperature control device. It is also found that the constant temperature depends upon the molecular weight of polyethylene glycol used. This makes it possible to obtain a heater which maintains a desired intrinsic constant temperature without any temperature control device.

Preparation of Narrowed

We have established the new method of fabricating high-J_c YBa₂Cu₃O_7-x (YBCO) nanobridges with high reproducibility. Nanobridges ranging in 30-400 nm wide were formed by using electron beam lithography. An ultra thin film of 2-3 nm-thick insulative YBCO was deposited after nanobridge formation for recovering the damaged films occurred in the process. The critical current density J_c was approximately 620 MA/cm² at 4.2 K in a width of 30 nm bridges, and increased by about two orders of magnitude in the different widths of J_c. The critical temperature T_c was 87 K, about the same as T_c of the film. The current-voltage characteristics showed a different curve from the conventional flux-flow type as the widths have been narrowed. Nanobridges developed in this study are expected to the applications for nano-SQUIDs or the optical input/output interfaces in single-flux-quantum circuits.

{\rm YBa}_{2}{\rm Cu}_{3}{\rm O}_{7-{\rm x}}

The work reported herein demonstrated that nanopipes can be formed via a surfactant effect, in which boron impurities preferentially migrate to semipolar and nonpolar facets. Approximately 3 μm-thick GaN layers were grown using halogen-free vapor phase epitaxy. All layers grown in pyrolytic boron nitride (pBN) crucibles were found to contain a high density of nanopipes in the range of 1010 to 1011 cm−2. The structural properties of these nanopipes were analyzed by X-ray rocking curve measurements, transmission electron microscopy, and three-dimensional atom probe (3DAP) tomography. The resulting 3DAP maps showed nanopipe-sized regions of boron segregation, and these nanopipes were not associated with the presence of dislocations. A mechanism for nanopipe formation was developed based on the role of boron as a surfactant and considering energy minima. A drastic reduction in the nanopipe density was achieved upon replacing the pBN crucibles with tantalum carbide-coated carbon crucibles. Consequently, we hav...

Nanobridges Down to 30 nm With Reduced Degradation

Here, we propose a halogen-free vapor phase epitaxy (HF-VPE) technique to grow bulk GaN single crystals. This technique employs the simplest reaction for GaN synthesis (reaction of Ga vapor with NH3) and can potentially achieve a high growth rate, a prolonged growth duration, a high crystal quality, and a low cost. The analyses of thick HF-VPE-GaN layers grown under optimized growth conditions revealed that high-quality crystals, both in terms of dislocation density and impurity concentration, are obtained at high growth rates of over 100 µm/h.

Nanopipe formation as a result of boron impurity segregation in gallium nitride grown by halogen-free vapor phase epitaxy

We report a developed single-flux-quantum (SFQ) circuit fabrication process for vertically-stacked interface-treated Josephson junctions by using high-temperature superconductor (HTS) and also report the 500 GHz operation of a toggle flip-flop (TFF). As the first trial of the circuit operation, we fabricated TFF circuits, because TFF is used as a benchmark circuit to indicate potential of the circuit operating speed. To develop the circuit fabrication process, we utilized the counter YBCO layer as a wiring layer. We obtained resistively-shunted-junction behavior of single junction fabricated by new process. In addition, we observed current-voltage characteristics at the input port and the output port of the TFF, and confirmed that the input voltage coincided with twice the output voltage up to 1.1 mV at 4.2 K, which corresponds to the correct operation up to 500 GHz. This frequency is the highest value in HTS circuits ever observed, which suggests the high potential of the vertically-stacked JJs for the circuit operation.

Halogen-free vapor phase epitaxy for high-rate growth of GaN bulk crystals

We investigated the effects of the post-oxidation annealing (POA) atmosphere on the electrical properties and interfacial roughness of SiO2 deposited on a 4H-SiC (0001) face and SiC. POA in ammonia (NH3) gave MOS capacitors with a lower interface trap density and n-channel MOSFETs with higher field-effect mobility than POA in nitrous oxide (N2O) or nitrogen (N2). In contrast, POA in N2O gave a lower interface trap density than POA in N2, but it gave the lowest field-effect mobility of all the samples. Cross-sectional TEM observations revealed that N2O POA gave a higher interfacial roughness than NH3 POA. We thus considered that N2O POA degraded the inversion-layer mobility due to increased roughness scattering.

Operation of Toggle Flip-Flop Circuits Up to 500 GHz Based on Vertically-Stacked High-Temperature Superconductor Josephson Junctions

We have fabricated vertically-stacked interface-treated Josephson junctions using YbBa/sub 2/Cu/sub 3/O/sub 7-x/ (YbBCO) as a counter electrode for improving the uniformity. We used YBCO for the base electrode. Most of the junctions fabricated on one chip exhibited resistively-shunted-junction (RSJ) characteristics. The properties of the junctions at 4.2 K were as follows: J/sub c/=1.0/spl times/10/sup 3/ A/cm/sup 2/ with a 1/spl sigma/ spread of 6.9%, and I/sub c/R/sub n/=0.5 mV with a 1/spl sigma/ spread of 5.4%. These spreads were improved compared with those of junctions with YBCO as a counter electrode. Furthermore, the normal conductance G/sub n/ of the junctions with the YbBCO counter electrode was independent of the temperature. Such characteristics have not been obtained for YBCO vertically-stacked interface-treated junctions. We speculate that this difference is attributed to the lattice mismatch between base-and counter-electrodes.

Effect of NH3 Post-Oxidation Annealing on Flatness of SiO2/SiC Interface

The GaN growth rate during halogen-free vapor phase epitaxy (HF-VPE) is significantly increased by the use of an evaporator made of a porosity-controlled TaC ceramic. A fin-shaped evaporator, which is immersed in a molten Ga source at temperatures above 1373 K, effectively pumps molten Ga by capillary action and provides a fivefold increase in the surface area of the source. This results in a 3–5 times increase in both the Ga supply rate and the GaN growth rate.

Vertically-stacked Josephson junctions using YbBa/sub 2/Cu/sub 3/O/sub 7-x/ as a counter electrode for improving uniformity

The authors have investigated the structure and the composition of the barrier in YBCO vertically-stacked-type interface-treated Josephson junctions by TEM and TEM-EDS. The barrier was formed by the Ar ion milling of the base YBCO electrode surface and the subsequent annealing. For a sample treated with accelerating voltage (V/sub acc/) of 1300 V, we observed Y/sub 2/O/sub 3/ phases in the barrier. In contrast, for a sample with V/sub acc/=700 V, we could observe few Y/sub 2/O/sub 3/ phases. Our TEM observation suggested that junctions with higher J/sub c/ fabricated with lower V/sub acc/ would have thinner and more uniform barriers. In addition, the composition of the barrier was Y-rich and Cu-poor, and such deviation decreased with decreasing V/sub acc/. These tendencies well correspond to the results for ramp-edge-type junctions reported so far.

Significant increase in GaN growth rate by halogen-free vapor phase epitaxy with porosity-controlled evaporator

In the present study, applying Al2O3 capping layer as suppressing layer of oxygen diffusion to SiC-MOS structures, we investigated the effect of Al2O3 layer as suppression of reoxidation at SiO2/SiC interface and decrease of Dit. We evaluated MOS capacitors which have SiO2/SiC and Al2O3/SiO2/SiC structure on 4H-SiC (0001) Si-face epitaxial wafers after post-oxidation anneal process (N2O:N2=1:9 [slm]) at temperatures ranging from 1000 °C to 1300 °C for 30min. The Al2O3/SiO2/SiC structure of reoxidation thickness, surface roughness and Dit are smaller than those of SiO2/SiC structure. These results show that the suppression of reoxidation during POA is important to improve the SiO2/SiC interfacial qualities.