Taizo Hoshino

Growth of Crack-Free 100mm-Diameter 4H-SiC Crystals with Low Micropipe Densities

The theromoelastic stress in post-growth SiC crystals has been investigated in order to suppress the cracks which were frequently observed in SiC crystals with larger diameters. Optimizing the temperature distribution in growing crystals lead to reduction of tensile stress components, and thus resulting in crack-free 100mm diameter SiC crystals with micropipe (MP) densities of 0.025/cm2. The concept of process optimization we established is confirmed to be effective to the growth of large diameter SiC crystals with mechanical stability.

Development of Lapping and Polishing Technologies of 4H-SiC Wafers for Power Device Applications

The development of lapping and polishing technologies for SiC single crystal wafers has realized the fabrication of an extremely flat SiC wafer with excellent surface quality. To improve the SiC wafer flatness, we developed a four-step lapping process consisting of four stages of both-side lapping with different grit-size abrasives. We have applied this process to lapping of 2-inch-diameter SiC wafers and obtained an excellent flatness with TTV (total thickness variation) of less than 3 μm, LTV (local thickness variation) of less than 1 μm, and SORI smaller than 10 μm. We also developed a novel MCP (mechano-chemical polishing) process for SiC wafers to obtain a damage-free smooth surface. During MCP, oxidizing agents added to colloidal silica slurry, such as NaOCl and H2O2, effectively oxidize the SiC wafer surface, and then the resulting oxides are removed by colloidal silica. AFM (atomic force microscope) observation of polished wafer surface revealed that this process allows us to have excellent surface smoothness as low as Ra=0.168 nm and RMS=0.2 nm.

Analysis of Basal Plane Bending and Basal Plane Dislocations in 4H-SiC Single Crystals

4H-SiC single crystals were grown by the physical vapor transport (PVT) growth method under different thermoelastic stress conditions, and the degree of basal plane bending in the crystals was characterized by the peak shift measurement of X-ray rocking curves. The results indicate that the degree of basal plane bending largely depends on the magnitude of the thermoelastic stresses imposed on the crystals during PVT growth. Quantitative analysis of basal plane bending revealed that the density of basal plane dislocations (BPDs) estimated from basal plane bending is much smaller than that obtained from defect-selective etching. It was also found that the BPD density is correlated with the threading screw dislocation (TSD) density in PVT-grown SiC crystals. These aspects of BPDs were discussed in terms of the BPD multiplication process triggered by the intersection of BPDs with a forest of TSDs extending along the c-axis.

Behavior of Basal Plane Dislocations in Hexagonal Silicon Carbide Single Crystals Grown by Physical Vapor Transport

The behavior of basal plane dislocations in hexagonal silicon carbide (SiC) single crystals grown by physical vapor transport (PVT) was investigated by defect selective etching and transmission electron microscopy (TEM). Oval-shaped etch pits on the etched vicinal (0001)Si surface due to basal plane dislocations were densely distributed around hollow-core threading screw dislocations (micropipes) and formed etch pit arrays perpendicular to the off-cut direction, indicative of the multiplication of basal plane dislocations around micropipes during crystal growth or post-growth cooling. Arrays of oval-shaped etch pits were also observed in the vicinity of small hexagonal etch pit rows due to threading edge dislocation walls, i.e., low angle grain boundaries (LAGBs). They were asymmetrically distributed across LAGBs, and TEM revealed that threading edge dislocations constituting LAGBs trapped basal plane glide dislocations. The interaction between basal plane dislocations and threading screw and edge dislocations extending along the c-axis in SiC crystals was modeled, and the characteristic behavior of basal plane dislocations in hexagonal SiC single crystals was discussed.

Time Sequential Evolutions of Optically-Induced Single Shockley Stacking Faults Formed in 4H-SiC Epitaxial Layers

Time-dependent evolutions of single and quadruple Shockley stacking faults (sSSF and 4SSF) in 4° off 4H-SiC epitaxial layers have been investigated. UV illuminations using an Hg-Xe lamp light source generate dissociations of basal plane dislocations (BPDs) into sSSFs whereas for 4SSFs no significant changes in shape occur. Detailed analyses of Photo-luminescence (PL) signals suggest that Si- and C-core partials have different PL spectrum distributions in the wavelength range larger than 750 nm, giving rise to images with different contrasts in PL mappings.

Stacking Fault Formation in Highly Nitrogen-Doped 4H-SiC Substrates with Different Surface Preparation Conditions

The stacking fault formation in highly nitrogen-doped n+ 4H-SiC single crystal substrates during high temperature treatment has been investigated in terms of the surface preparation conditions of substrates. Substrates with a relatively large surface roughness showed a resistivity increase after annealing at 1100°C, which was confirmed to be caused by the formation and expansion of double Shockley-type basal plane stacking faults in the substrates. The occurrence of the stacking faults largely depended on the surface preparation conditions of the substrates, which indicates that the primary nucleation sites of stacking faults exist in the near-surface regions of substrates. In this regard, mechano-chemically polished (MCP) substrates with a minimum surface roughness (< 0.3 nm) exhibited no resistivity increase and very few stacking faults after annealing even when the nitrogen concentration of the substrates exceeded 1×1019 cm-3.

Improvement of Surface Roughness for 4H-SiC Epilayers Grown on 4° Off-Axis Substrates

The epitaxial growth process was optimized in order to obtain good surface morphology for epilayers grown on 4˚ off-axis substrates. The optimization was carried out from growth temperatures and gas chemistry including C/Si ratio. Step-bunching was significantly suppressed by the optimized process and a surface roughness Ra of 0.2 nm was achieved. Etch pit density evaluation by KOH etching indicated that the basal plane dislocations were reduced to less than 50 cm-2 by the use of 4˚ off-axis substrates. Photoluminescence evaluation showed that the epilayer grown by the optimized process had a better crystalline quality than that grown by a standard process. Schottky diodes fabricated on the epilayer by the optimized process represented the ideality factor n of 1.01 and the barrier height of 1.67eV. These results demonstrate that high quality epilayers with smooth surfaces comparable to those on 8˚off-axis substrates were obtained on 4˚off-axis substrates.

Structural Analysis of Dislocations in Highly Nitrogen-Doped 4H-SiC Substrates

Dislocations in highly nitrogen-doped (N > 1×1019 cm-3) low-resistivity ( < 10 mcm) 4H-SiC substrates were investigated by photoluminescence imaging, synchrotron X-ray topography, and defect selective etching using molten KOH. The behavior of dislocations is discussed particularly in terms of their glide motion in the presence of a high concentration of nitrogen. The results indicate that nitrogen impurities up to mid 1019 cm-3 concentration do not show any discernible influence on the glide behavior of basal plane dislocations (BPDs) in 4H-SiC crystals grown by physical vapor transport (PVT) method.

4H-SiC Epitaxial Growth on Carbon-Face Substrates with Reduced Surface Roughness

4H-SiC epitaxial layers on Carbon-face (C-face) substrates were grown by a low-pressure hot-wall type chemical vapor deposition system. The C-face substrates were prepared by fine mechanical polishing using diamond abrasives with the grit size of 0.25 %m and in-situ HCl etching at 1400°C, which produced surface roughness of 0.27 nm. The use of the smooth substrates made it possible to decrease the substrate temperature and specular surface morphologies were realized at C/Si ratios of 1.5 or less both for a substrate temperature of 1550°C and for that of 1500°C. Surface roughness of 0.26 nm and the residual donor concentration of 6.7×1014 cm-3 were obtained for a C-face epitaxial layer grown at a C/Si ratio of 1.5 and at a substrate temperature of 1550°C. Schottky barrier diodes were fabricated on a non-doped C-face epitaxial layer grown at 1500°C and it was verified that a high quality metal-semiconductor interface was formed on the epitaxial layer.

Annealing Temperature Dependence of Dislocation Extension and its Effect on Electrical Characteristic of 4H-SiC PIN Diode

In this study, we investigated the annealing temperature dependence of dislocation extension in an ion-implanted region of a 4H-silicon carbide (SiC) C-face epitaxial layer, revealing that a high temperature annealing led to dislocation formation. We also investigated the current-voltage (I-V) characteristics of a 4H-SiC PIN diode with and without these extended dislocations. We demonstrated that the forward biased I-V characteristics of samples with extended interfacial dislocations have a kink at lower current regions.