Taizo Sato

Cache memory and data processor including instruction length decoding circuitry for simultaneously decoding a plurality of variable length instructions

Hierarchical cache memory system and method for controlling data coherency between a primary and a secondary cache

Blocks and bits sequence reversing device using barrel shift

Memory controller and a cache for accessing a main memory, and a system and a method for controlling the main memory

System for controlling an internally-installed cache memory

Data processing unit including a variable bit length bypass circuit

Information processing apparatus with parallel instruction decoding

Processing device for buffering sequential and target sequences and target address information for multiple branch instructions

Processor with a respective latch provided for each pipelined stage to transfer data to the pipeland stages

Computer with high-speed context switching