Yoshimasa Takebe

A vector coprocessor architecture for embedded systems

We developed a DSP for wireless base-band processing on handheld devices. The DSP is composed of a scalar CPU and a vector unit. The architecture of the vector unit inherits that of vector processors for super computers, and we customized it for embedded systems. We evaluated the processor using several programs. The evaluation showed that our DSP performs 40 times faster than scalar CPU. The peak performance is 12GOPS@250MHz.

A novel processor design flow using processor description language applied to a vector coprocessor

We have developed a vector coprocessor for a wireless baseband SoC for mobile devices using processor description language. The design of the vector coprocessor is highly-complex and it requires a lot of design time and costs with a conventional design flow. To address this problem, we developed an architecture design flow with an untimed model and a performance estimator. We achieved 4.5 times better design efficiency compared to a conventional implementation design flow with a timed model. As a result, we were able to reduce design and optimization time dramatically.