Takahiro Kawasaki

Hybrid metrology solution for 1X node technology

The accelerated pace of the semiconductor industry in recent years is putting a strain on existing dimensional metrology equipments (such as CDSEM, AFM, Scatterometry) to keep up with ever-increasing metrology challenges. However, a revolution appears to be forming with the recent advent of Hybrid Metrology (HM) - a practice of combining measurements from multiple equipment types in order to enable or improve measurement performance. In this paper we extend our previous work on HM to measure advanced 1X node layers - EUV and Negative Tone Develop (NTD) resist as well as 3D etch structures such as FinFETs. We study the issue of data quality and matching between toolsets involved in hybridization, and propose a unique optimization methodology to overcome these effects. We demonstrate measurement improvement for these advanced structures using HM by verifying the data with reference tools (AFM, XSEM, TEM). We also study enhanced OCD models for litho structures by modeling Line-edge roughness (LER) and validate its impact on profile accuracy. Finally, we investigate hybrid calibration of CDSEM to measure in-die resist line height by Pattern Top Roughness (PTR) methodology.

Three-dimensional profile extraction from CD-SEM image and top/bottom CD measurement by line-edge roughness analysis

A new method for calculating critical dimension (CDs) at the top and bottom of three-dimensional (3D) pattern profiles from a critical-dimension scanning electron microscope (CD-SEM) image, called as “T-sigma method”, is proposed and evaluated. Without preparing a library of database in advance, T-sigma can estimate a feature of a pattern sidewall. Furthermore, it supplies the optimum edge-definition (i.e., threshold level for determining edge position from a CDSEM signal) to detect the top and bottom of the pattern. This method consists of three steps. First, two components of line-edge roughness (LER); noise-induced bias (i.e., LER bias) and unbiased component (i.e., bias-free LER) are calculated with set threshold level. Second, these components are calculated with various threshold values, and the threshold-dependence of these two components, “T-sigma graph”, is obtained. Finally, the optimum threshold value for the top and the bottom edge detection are given by the analysis of T-sigma graph. T-sigma was applied to CD-SEM images of three kinds of resist-pattern samples. In addition, reference metrology was performed with atomic force microscope (AFM) and scanning transmission electron microscope (STEM). Sensitivity of CD measured by T-sigma to the reference CD was higher than or equal to that measured by the conventional edge definition. Regarding the absolute measurement accuracy, T-sigma showed better results than the conventional definition. Furthermore, T-sigma graphs were calculated from CD-SEM images of two kinds of resist samples and compared with corresponding STEM observation results. Both bias-free LER and LER bias increased as the detected edge point moved from the bottom to the top of the pattern in the case that the pattern had a straight sidewall and a round top. On the other hand, they were almost constant in the case that the pattern had a re-entrant profile. T-sigma will be able to reveal a re-entrant feature. From these results, it is found that T-sigma method can provide rough cross-sectional pattern features and achieve quick, easy and accurate measurements of top and bottom CD.

How to measure a-few-nanometer-small LER occurring in EUV lithography processed feature

For EUV lithography features we want to decrease the dose and/or energy of CD-SEM’s probe beam because LER decreases with severe resist-material’s shrink. Under such conditions, however, measured LER increases from true LER, due to LER bias that is fake LER caused by random noise in SEM image. A gap error occurs between the right and the left LERs. In this work we propose new procedures to obtain true LER by excluding the LER bias from the measured LER. To verify it we propose a LER’s reference-metrology using TEM.

Key points to measure accurately an ultra-low LER by using CD-SEM

Metrology of line-edge roughness (LER) or line-width roughness (LWR) reduced less than a few nanometers in recent advanced-process is one of issues because measured LER is strongly dependent on measurement conditions such as magnification and beam dose. It may happen that different organizations measure different LERs on an identical sample. By using an ultra-low LER sample we demonstrate intolerable change of measured LER between with and without necessary key-points in the measurement conditions of critical-dimension secondary electron microscope (CD-SEM).

Compensation of CD-SEM image-distortion detected by View-Shift Method

Local-distortion of CD-SEM image can be detected and compensated by a unique technique: View-Shift method. As design rule of semiconductor device is getting shrunk, metrology by critical dimension scanning electron microscope (CD-SEM) is not only for measuring dimension but also shape, such as 2D contour of hot-spot pattern and OPC calibration-pattern. Accuracy of the shape metrology is dependent on the local image-distortion that consists of two components: magnification distortion and shape distortion. The magnification distortion can be measured by pitchcalibration method, that measures pitch of an identical line pattern at a lot of locations in image. However, this method cannot measure the shape distortion, that is for instance, bending of a uniform-width line. To measure accurately and quickly the image-distortion, we invented the View-Shift method, in which images of uniquetexture sample are taken before and after an image-shift by about 100nm. Between the two images we measure displacements of the unique-textures found at each grid-point spread over the image. Variation of the local displacements indicates the local image-distortion. In this work, we demonstrate a method to compensate the image-distortion detected by the View-Shift method. Due to the image-distortion, edge-points determined in SEM-image have already been dislocated. Such dislocation can be relocated to compensate the detected local-distortion. Onsite and on-demand compensation right before CD-SEM measurement for process monitoring is possible because we can quickly apply the View-Shift method and complete the compensation in a few minutes.

CD-SEM image-distortion measured by view-shift method

As the design rule for semiconductor device shrinks, metrology for the critical dimension scanning electron microscope (CD-SEM) is not only for measuring the dimension but also the shape, such as 2D contour of hot-spot pattern and OPC calibration-pattern. Accuracy of the shape metrology is dependent on distortion of CD-SEM image. The distortion of magnification in horizontal direction (i.e. x-direction) can be measured by pitch-calibration method, that measures pitch of identical vertical line patterns while view-shifting the identical pitch in x-direction. However, the number of measurement point could not be sufficient because this method requires long measurement time. Not only the horizontal magnification but also vertical magnification (i.e. y-direction) and shear deformation (i.e. distortion of shape) are necessary to keep highly accurate measurement. In this paper we introduce the view-shift method for quick and accurate measurement of the image-distortion. From using this method, both local distortion of magnification and shape can be measured in horizontal and vertical directions at once. Firstly, two SEM-images of evaluation sample are taken. The sample should have a lot of unique features, e.g. Textured-Silicon. View-shift about one ninth of the image size should be done by two images, and There are a lot of unique features in overlapped region between two images. As distribution of the unique features, displacement between two images indicates the local image-distortion. The dislocation of sample contour from distortion is estimated from the local-distortion. The image-dislocation on a tool evaluated in this paper is less than 0.5 nm. It is a tolerated size for current device process. However, it could be increased under the noisy external environment.