Takahiro Naito

Ultra-Thin 3D-Stacked SIP Formed using Room-Temperature Bonding between Stacked Chips

The wire bonding technique has been used for conventional 3D-stacked packages. However, it requires an additional bonding area on the substrate and long wires for connecting a chip to a substrate. In this study, a method is described for interconnecting stacked chips using through-hole electrodes. Electrical interconnection between the chips is achieved by simply applying a compressive force at room temperature to a conventional chip with multiple gold stud bumps. The basic concept of the proposed method was validated using test samples with quasi-through-hole electrodes. Application of chip-to-chip interconnection to a conventional 3D-stacked system-in-package (SiP) with an microprocessing unit (MPU) chip and an synchronous DRAM (SDRAM) chip reduced the package thickness to less than 0.5 mm from 1.25 mm and the number of layer in the package substrate to two (thickness less than 0.2 mm) from six (0.45 mm). The wiring distance between stacked chips is minimized by using an interposer chip. We formed through-hole electrodes in a 30-mum-thick silicon wafer and determined that the measured leakage with plasma CVD of SiO2 met our target specification for the electrical insulation between through-hole electrodes. Use of this method should facilitate the production of ultra-slim, high-performance SiP

Low-cost through-hole electrode interconnection for 3D-SiP using room-temperature bonding

To verify the operation of three-dimensional SiP with through-hole electrode interconnections, we manufactured a prototype of a 3D-SiP sample composed of a MCU, an interposer, and a synchronous DRAM (SDRAM) chip using a proposed mechanical caulking operation. A new electrode design of LSI for through-hole electrode interconnection is important for establishing a stable mass-production process. By using this technology, the package thickness can be 1.0 mm or less even in ten-chip layers, compared with two-chip layers using wire bonding, which are approximately 1.25-mm thick

Through-Silicon via Interconnection for 3D Integration Using Room-Temperature Bonding

One approach to 3D technology is chip stacking using through-silicon vias (TSVs). Interconnects in a 3D assembly are potentially much shorter than in a 2D configuration, allowing for faster system speed and lower power consumption. However, it is extremely important to use cost-effective process technologies in practical use. Therefore, in our study, we propose a basic concept for interconnecting stacked chips with TSVs using a cost-effective process technology. The principal feature is to use a ldquomechanical-caulkingrdquo technique, which has been used widely in the mechanical-engineering field, enabling 3D interconnections between stacked chips. This makes it possible to interconnect them by only applying compressive force at room temperature. This paper presents the results obtained by using mechanical-caulking connections at room temperature accomplished by manufacturing a prototype of a chip-stacked package with TSV interconnections. A 3D-SiP composed of an existing MCU, an interposer, and an SDRAM chip with TSV interconnections was also manufactured. However, a customized design, assuming TSV interconnections in the existing MCU, needs to be introduced for practical use to achieve SiO2 etching with shorter turn around time (TATs) and high TSV yields of more than 99%.

Characterization of MOS transistor after through-hole electrode fabrication and 3D-assembly by mechanical caulking

Three-dimensional (3D) packaging technology has recently been developed for System in Package applications. The 3D packaging technology with through-hole electrodes has been receiving an especially great deal of attention because through-hole electrodes technology results in compact and high-performance systems.

Highly reliable and low-cost multi-chip module composed of wafer process packages

A high-performance. low-cost, and highly reliable multichip module (MCM) was developed. It is composed of a MPU and a synchronous DRAM [i.e., wafer process packages (WPPs)] on a substrate, To reduce the cost of the MCM, a low-cost FR-4 base is used a substrate on which the WPPs are mounted. Since the mismatch between the thermal expansion coefficients (TEC) of the MPU and DRAM chips and the substrate increases, thermal deformation due to the mismatch may cause cracking of the chip or decrease the life of the solder joints between the MCM and a FR-4 base motherboard. To minimize the stress caused by thermal deformation in the MCM and, thus, to improve its reliability, the structure of the MCM was therefore optimized by finite element analysis (FEA). The FEA results show that thermal stresses in both the chips and the solder bumps are a function of the ratio of chip thickness (tc) and substrate thickness (ts), i.e., tclts, and these stresses decrease when tclts is decreased. Furthermore, thermal-cycling test results show that MCM reliability is assured when tclts is 0.5 or less. A MCM with tclts of 0.4, including a margin of safety, was developed. It was found that the life of this MCM is over 1000 cycles (no chip cracking and no solder joint failure) under thermal-cycling between -55°C and 125°C.