Naotaka Tanaka

Ultra-high-density interconnection technology of three-dimensional packaging

Abstract The study of 20-μm-pitch interconnection technology of three-dimensional (3D) packaging focused on reliability, ultrasonic flip–chip bonding and Cu bump bonding is described. The interconnection life under a temperature cycling test (TCT) was at an acceptable level for semiconductor packages. Failure analysis and finite element analysis revealed the effect of material properties. Basic studies on ultrasonic flip–chip bonding and very small Cu bump formation were investigated for low-stress bonding methods. The accuracy of ultrasonic flip–chip bonding was almost the same level as that of thermocompression bonding and the electrical connection was also confirmed. Atomic-level bonding was established at the interface of Au bumps. For Cu bump bonding, a dry process was applied for under bump metallurgy (UBM) removal. Electroless Sn diffusion in Cu was investigated and the results clarified that the intermetallic layer was formed just after plating. Finally, we succeeded in building a stacked chip sample with 20-μm-pitch interconnections.

Micro Cu Bump Interconnection on 3D Chip Stacking Technology

The three-dimensional (3D) chip stacking LSI technology under development at the Association of Super-Advanced Electronic Technologies (ASET) is a new packaging technology to realize high-density and high-speed transmission, and superfine flip-chip bonding technologies in 20-µm-pitch microbumps on Cu through-via (TV) are substantial technologies. As for advanced bonding technology, Cu bump bonding (CBB) utilizing Sn alloy is a simple process to connect Cu TVs directly without the formation of bumps on the device back surface, and the influence of the intermetallic compound (IMC) on the minute interconnection focusing on the bondability and reliability was verified, and the following results were obtained. The IMC state formed at the bonding interface depended on bonding temperature, and was confirmed as multilayered Cu6Sn5 and Cu3Sn at 240°C, and single-layered Cu3Sn at 350°C. The IMC state is the governing factor of bondabilities of Cu bump interconnection in a 20-µm-pitch. The electroresistance value of the Cu bump interconnection was approximately 0.45 Ω, and no significant difference was confirmed under each condition. Youngs modulus values of IMC (Cu6Sn5:112.6 GPa and Cu3Sn:132.7 GPa) were obtained by the nano-indentation test. The Sn-Ag layer as bonding material should be reduced to Cu-Sn IMC, and a low-rigid resin was preferable in terms of interconnection reliability based on the results of finite element method (FEM) analysis. Finally, the vertical interconnections utilizing CBB were formed, and the increase in electrical resistance by stacking one TV chip was approximately 0.03 Ω. Therefore, sufficient electrical vertical interconnection of Cu TV in a 20-µm-pitch was performed.

Mechanical effects of copper through-vias in a 3D die-stacked module

Mechanical effects of copper through-vias formed in silicon dies in a three dimensional module, in which four bare-dies with copper through-vias are vertically stacked and electrically connected through the copper-vias and metal bumps, were numerically and experimentally studied. To examine the mechanical effects caused by the existence of the copper through-vias in a rigid silicon-chip, a series of stress analyses, related simple mechanical tests, and reliability tests were carried out. All these results show that the copper through-via has unique effects on the stress distribution caused by thermal mismatch and on the interconnection reliability in the 3D die-stacked module. In particular, it was found that the developed micro copper through-via is reliable because the stress distribution due to thermal load is close to the hydrostatic pressure condition, and enhances chip-to-chip interconnection reliability because the copper-via restrains the plastic deformation of a gold bump during temperature cycling.

Au Bump Interconnection in 20 µm Pitch on 3D Chip Stacking Technology

The three-dimensional (3D) chip stacking LSI technology under development in Association of Super-Advanced Electronic Technologies (ASET) is a new packaging technology for realizing high-density and high-speed transmission, and superfine flip-chip bonding technologies utilizing 20-µm-pitch micro bumps on Cu through hole electrodes are substantial technologies. There are two key technical issues involved in realizing the 3D chip stacking LSI. One is the provision of the sufficient interconnections, which have low resistivity and which are absolutely connected. Another is the reduction of the thermal stress of the micro bumps by providing encapsulated resin between devices. Regarding the metallurgically stable and low electrical resistance interconnections, electroplated Au bump bonding in 20-µm-pitch by thermo compression bonding process was evaluated on the chip-on-chip(COC) structure. First, the softening of the Au bump by annealing was confirmed, and was expected to decrease the bonding stress of the under bump structure. Second, the lower limit bonding conditions were confirmed to be a bonding force of 24.5 N at 350°C, and the electrical resistance was confirmed to be stable at about 0.55 Ω. The mechanism of Au–Au thermo compression bonding with the solid phase diffusion across the boundary was confirmed. Finally, the life of the 20-µm-pitch interconnection with the underfillresin containing the hyperfine filler particles under temperature cycling tests (TCT) was more than 1000 cycles, which is an acceptable level for a semiconductor package. This research will enable the realization of 3D chip stacking LSI in the near future which features scalability and high performance. The subjects are the verification of the appropriate bump dimensions in order to further improve the reliability and the realization of the interconnection reliability on 3D chip stacking LSI.

A New Method for Measuring Adhesion Strength of IC Molding Compounds

Adhesion strength evaluation of molding compounds is a critical issue in structural design and material selection for IC plastic packages. However, since conventional adhesion tests can only give apparent adhesion strengths, which include the effect of residual stress, their results cannot be used for design purposes. This paper proposes a new strength evaluation method which can experimentally separate residual stress from adhesion strength. In this method, three-point bending tests of ENF specimens are performed in both directions. Residual stress is then cancelled by simply averaging the apparent strengths for both directions. The method’s validity is verified by experiments and stress analyses of specimens composed of an IC molding compound and Alloy 42 lead frame material. Adhesion strength is expressed in terms of the stress intensity factor of the interface crack. It is confirmed that constant strengths can be obtained independently of specimen dimensions.

Ultra-Thin 3D-Stacked SIP Formed using Room-Temperature Bonding between Stacked Chips

The wire bonding technique has been used for conventional 3D-stacked packages. However, it requires an additional bonding area on the substrate and long wires for connecting a chip to a substrate. In this study, a method is described for interconnecting stacked chips using through-hole electrodes. Electrical interconnection between the chips is achieved by simply applying a compressive force at room temperature to a conventional chip with multiple gold stud bumps. The basic concept of the proposed method was validated using test samples with quasi-through-hole electrodes. Application of chip-to-chip interconnection to a conventional 3D-stacked system-in-package (SiP) with an microprocessing unit (MPU) chip and an synchronous DRAM (SDRAM) chip reduced the package thickness to less than 0.5 mm from 1.25 mm and the number of layer in the package substrate to two (thickness less than 0.2 mm) from six (0.45 mm). The wiring distance between stacked chips is minimized by using an interposer chip. We formed through-hole electrodes in a 30-mum-thick silicon wafer and determined that the measured leakage with plasma CVD of SiO2 met our target specification for the electrical insulation between through-hole electrodes. Use of this method should facilitate the production of ultra-slim, high-performance SiP

Evaluating IC-package interface delamination by considering moisture-induced molding-compound swelling

We have determined the influence of moisture soaking conditions on true adhesion strength measured by our previously developed method. The drop in true adhesion strength of a specimen that absorbed moisture at 50/spl deg/C is about 50% less than that of a specimen at 85/spl deg/C. This result suggests that the true adhesion strength depends on not only the moisture content but also the moisture absorption temperature. Therefore, we think that the general moisture condition (85/spl deg/C/85%) causes more damage to plastic integrated circuit (IC) packages than that of moisture absorption at room temperature. We also evaluated interface delamination in a moisture-absorbed package by considering the swelling of the molding compound due to moisture absorption. The predicted interface delamination agrees well with the experimental data for moisture-soaked packages.

Low-cost through-hole electrode interconnection for 3D-SiP using room-temperature bonding

To verify the operation of three-dimensional SiP with through-hole electrode interconnections, we manufactured a prototype of a 3D-SiP sample composed of a MCU, an interposer, and a synchronous DRAM (SDRAM) chip using a proposed mechanical caulking operation. A new electrode design of LSI for through-hole electrode interconnection is important for establishing a stable mass-production process. By using this technology, the package thickness can be 1.0 mm or less even in ten-chip layers, compared with two-chip layers using wire bonding, which are approximately 1.25-mm thick

Evaluation of interface delamination in IC packages by considering swelling of the molding compound due to moisture absorption

Adhesion strength evaluation of molding compounds is a critical issue in both structural design and material selection of plastic IC packages. We previously proposed a new adhesion test method that can separate residual stress from adhesion strength, and we confirmed that the measured true adhesion strength can be applied to the quantitative prediction of interface delamination in a dry package. This paper describes the influence of moisture absorbing conditions on true adhesion strength determined by this method. The drop of true adhesion strength of a specimen that has absorbed moisture at 50/spl deg/C is about 40 percent of that of a specimen at 85/spl deg/C. This suggests that the general moisture condition (85/spl deg/C/85%) accelerates the damage to plastic IC packages when compared to the case of moisture absorption at room temperature. We also evaluated interface delamination in a moisture-absorbed package by considering the swelling of the molding compound due to moisture absorption. The predicted results agree well with the experimental data for moisture-absorbed packages.

Through-Silicon via Interconnection for 3D Integration Using Room-Temperature Bonding

One approach to 3D technology is chip stacking using through-silicon vias (TSVs). Interconnects in a 3D assembly are potentially much shorter than in a 2D configuration, allowing for faster system speed and lower power consumption. However, it is extremely important to use cost-effective process technologies in practical use. Therefore, in our study, we propose a basic concept for interconnecting stacked chips with TSVs using a cost-effective process technology. The principal feature is to use a ldquomechanical-caulkingrdquo technique, which has been used widely in the mechanical-engineering field, enabling 3D interconnections between stacked chips. This makes it possible to interconnect them by only applying compressive force at room temperature. This paper presents the results obtained by using mechanical-caulking connections at room temperature accomplished by manufacturing a prototype of a chip-stacked package with TSV interconnections. A 3D-SiP composed of an existing MCU, an interposer, and an SDRAM chip with TSV interconnections was also manufactured. However, a customized design, assuming TSV interconnections in the existing MCU, needs to be introduced for practical use to achieve SiO2 etching with shorter turn around time (TATs) and high TSV yields of more than 99%.