Takahiro Tsukamoto

Morphology of Graphene on Step-Controlled Sapphire Surfaces

Graphene attached on a sapphire surface with regularly ordered step-terrace structure was observed using atomic force microscopy (AFM). We found that graphene tightly adheres to a sapphire surface and the buried step structure on the sapphire surface was clearly observed on the graphene surface. Height of a single-layer graphene was estimated to be approximately 0.36 nm on sapphire surface, which is in good agreement with the theoretical height. These results indicate that sapphire is suitable for the substrate that supports graphene because we can obtain undistorted graphene that is tightly fixed on a substrate surface.

'Graphene-on-insulator' fabricated on atomically controlled solid surfaces

Graphene or few layer graphene (FLG) was attached on a single-crystalline sapphire surface on which a regularly ordered step/terrace structure was formed. The height of graphene from the substrate surface was observed to be about 0.35 nm, which is almost equal to the layer spacing of graphite. On the attached graphene or FLG surface, the step/terrace structure originating from the sapphire surface was clearly observed because the graphene flake tightly adhered to the sapphire surface. FLGs were etched by a reaction between carbon of the FLG and H2 gas at 900 °C using Fe nanoparticles as catalysts. When a FLG flake is thick, the etching direction is subject to the crystallographic directions of graphene. As the FLG is thinner than 6 nm, strain induced on the FLG surface by the step/terrace structure of the substrate surface influences the etching direction, and etching along a buried step occurs when the Fe nanoparticle size is small. The etching directions of FLG can be controlled by the ordered atomic step arrangement on sapphire surfaces owing to the surface flatness and tight adhesion of graphene to the surface.

p-Cu2O/SiCxOy/n-SiC/n-Si memory diode having resistive nonvolatile memory and rectifying behaviors

We have proposed a pn memory diode having a p-Cu2O/SiCxOy/n-SiC/n-Si diode structure with a SiCxOy layer formed between the pn semiconducting layers. The memory diode shows both resistive-nonvolatile-memory and rectifying behaviors, which are suited for the theoretically densest cross-point memory array. The forward bias current switches between high and low currents corresponding to low- and high-resistance states, respectively. Experimental results suggest that the change in the state is related to the nonexistence or existence of negative charges generated by electrons trapped in the intermediate SiCxOy oxide layer. This memory also exhibits good endurance characteristics of more than 105 resistance-switching cycles.

Graphene Etching on Well-Defined Solid Surfaces

Graphene is a two-dimensional material with hexagonal carbon network, and multilayer of graphene has been well-known as graphite. In 2004, it was reported that single-layer graphene can be exfoliated from graphite and observed using an optical microscope when a graphene sheet is attached on a 300 nm-thick SiO2/Si wafer (Novoselov et al., 2004). Graphene exhibits an extremely high mobility, 200,000 cm2/Vs, which is 200 times as fast as that of Si. This high mobility was theoretically expected and then a mobility of 230,000 cm2/Vs was experimentally observed in a suspended graphene sheet (Bolotin et al., 2008). Since the sp2 bonding of carbon is very strong, a mechanically and chemically stable twodimensional network with few defects is realized in spite of an expectation that an atomic layer would be intrinsically unstable (Stolyarova et al., 2007). Owing to the small weight of carbon atom and the strong bonding between the atoms, thermal conductivity of graphene is in the highest group in the materials (Balandin et al., 2008). These features are effectively utilized when graphene is applied to electronic devices. Up to now, many reports have shown that graphene electronics is very promising for post-Si devices, but serious problems are also pointed out. For example, compatibility of high-quality graphene and wafer-scale processing is a big challenge. Although high-quality graphene can be obtained by exfoliation of graphene flakes from graphite, its size is small and the position control is almost impossible. Wafer-scale preparation of graphene sheets and their processing can be realized by epitaxial graphene on SiC (Berger, et al., 2004), chemical vapour deposition of graphene on a metal substrate (Sutter et al., 2008; Bae et al., 2010; Li et al., 2009), or coating of graphene oxide (Eda et al., 2008; Li et al., 2008). However, the quality of those graphene is not sufficient for high-performance devices. In this article, we show our recent results about substrate engineering toward graphene integrated devices. We first describe properties and features of graphene on solid surfaces and then show strategy about etching of graphene, where “etching” is used for cutting of graphene sheets through chemical reactions. Based on this background, we show our experimental results about tight attachment of graphene onto oxide substrates, such as sapphire and titania, and characterize the interface properties between the graphene sheet and the substrate surface. Finally, we show processing of graphene sheets attached on the sapphire surfaces using the atomic structures on the substrate surface as templates. Here, we would like to emphasize that the interface properties between the graphene sheet and the substrate is particularly important and that etching and local properties of the graphene

p-Cu2O/SiO x /n-SiC/n-Si memory diode fabricated with room-temperature-sputtered n-SiC and SiO x

We investigated low-temperature fabrication processes for our previously proposed pn memory diode with a p-Cu2O/SiC x O y /n-SiC/n-Si structure having resistive nonvolatile memory and rectifying behaviors suitable for a cross-point memory array with the highest theoretical density. In previous fabrication processes, n-SiC was formed by sputtering at 1113 K, and SiC x O y and p-Cu2O were formed by the thermal oxidation of n-SiC and Cu at 1073 and 473 K, respectively. In this study, we propose a pn memory diode with a p-Cu2O/SiO x /n-SiC/n-Si structure, where n-SiC and SiO x layers are deposited by sputtering at room temperature. The proposed processes enable the fabrication of the pn memory diode at temperatures of not more than 473 K, which is used for the formation of p-Cu2O. This memory diode exhibits good nonvolatile memory and rectifying characteristics. These proposed low-temperature fabrication processes are expected to expand the range of fabrication processes applicable to current LSI fabrication processes.

Low-temperature fabrication technologies of Si solar cell by sputter epitaxy method

We applied an epitaxial n+-type Si emitter layer grown on a p-type Si substrate by our environmentally-light-load sputter epitaxy method using RF magnetron sputtering without dopant activation annealing for a Si solar cell. We also applied low-temperature cleaning of the substrate with a hydrogen-fluoride treatment at room temperature prior to the emitter layer growth instead of the conventionally used high-temperature thermal cleaning under vacuum condition. In addition, by our sputter epitaxy method, we determined the optimum temperature for the emitter growth. An emitter layer with good crystallinity is obtained, and the solar cell, formed with an emitter layer grown at the optimum growth temperature of 410 °C, exhibits an energy conversion efficiency of 12.3% in 100% aperture ratio equivalent without a texture or an antireflection coat. By the above low-temperature processes, a solar cell can be fabricated with process temperatures below 410 °C, which exhibits low temperature processes.

Planar electron-tunneling Si/Si0.7Ge0.3 triple-barrier resonant tunneling diode formed on undoped strain-relaxed buffer with flat surface

We demonstrated a planar electron-tunneling Si/Si0.7Ge0.3 triple-barrier (TB) resonant tunneling diode (RTD) formed via a channel layer on an undoped strain-relaxed quadruple-Si1−xGex-layer (QL) buffer. Compared with a conventional vertical Si/Si0.7Ge0.3 TB RTD formed on a heavily doped QL buffer, the dislocation density is low, the surface is flat, and the resonance current density is much larger. These observations, together with analyses of current–voltage (I–V) curve fitting to the physics-based analytical expression, suggest that the enhanced I–V characteristics in the planar RTD are related to decreases in the number of crystalline defect states and the structural and potential fluctuations.