Takamichi Maeda

Development of copper wire bonding application technology

The continuous forming of oxide-free, stable, spherical copper balls which has been realized by blowing a reducing gas over the copper wire during copper ball formation (sparkling) is described. The prevention of chip damage resulting from hard copper wire, including underpad cracking and silicon cratering, by the double-load wire bonding technology is discussed; this technology can minimize chip damage from wire bonding stress because the bonding load is decreased during ultrasonic power oscillation. It was confirmed that copper wires have a reliability equivalent to that of gold wires. The double-load wire bonding technology makes it possible to use copper wires in MOS LSI devices on a commercial basis. >

Causes of cracks in SMD and type specific remedies

Packages used with surface mount devices (SMDs) have the unique reliability problem of package cracks produced by soldering stress. Package cracks are classified into three distinct modes, depending on the location of origin and direction of spread. In type I, the crack originates on one edge of the die pad and spreads to the bottom side of the package. In type II, the crack originates on one edge of the die pad and spreads to the top surface of the package. In type III, the crack spreads from an edge of the chip to the top surface of the package. To remedy this cracking problem, it is necessary to determine the type of cracking that may occur, and take a countermeasure specific to each type. The authors investigated possible causes for each type of package crack, and techniques for crackproof package design optimized for individual crack types were developed. The following three techniques for anticrack package design, or a combination of two or more, have proved effective: (1) molding compound with improved resistance to soldering heat, (2) polyimide coating on the back side of the die pad, and (3) improved lead frame design.<<ETX>>

Development of ultra-thin surface mounting IC package (0.8 mm thick TQFP)

A TQFP (thin quad flat package) with a package size of 10*10 mm and a maximum package thickness of 0.8 mm has been developed to meet the need for lower profiles in surface-mounting packages. For a package thickness of 1.0 mm, the conventional lead-frame thickness and chip thickness are sufficient. However, when the package thickness is reduced to 0.8 mm, a reduction in at least one of the conventional thicknesses is absolutely essential. Therefore, by reducing the thickness of only part of the die-pad portion of the lead frame through the use of chemical etching to approximately 1/2 to 2/3, the resin thickness above the chip and below the die pad is ensured. A low-loop wire bond with a maximum of 0.14 mm was achieved by optimizing the wire material and wire-bond conditions. Ultrathin molding was achieved by improving the fluid characteristics of the resin and by ensuring the resin-fluid balance within the cavity. Package cracking and degraded moisture resistance were evaluated using a 4-Mbit mask ROM. After subjecting it to 85 degrees C and 75% RH for 72 h, no problems were noticed while soldering at 240 degrees C maximum with infrared reflow.<<ETX>>

Development of 0.45 mm thick Ultra-Thin Small Outline Package (UTSOP)

The authors developed an Ultra-Thin Small Outline Package (UTSOP) with a package thickness of 0.45 mm. In spite of the fact that it is a significant reduction relative to conventional TSOPs (1.0 mm thick), the inner leads of the lead frame can be bonded to the electrodes on the chip with gold wire as with a conventional plastic package. It is feasible since the lead that supports the chip through insulating tape (support lead) is placed on the top side of the chip. Establishing molding technology and overcoming problems such as warping of the package or chip during assembly were key points in the development of the UTSOP. The UTSOP retains the same level of reliability as a TSOP.<<ETX>>